Signal Integrity & Noise Analysis: Strong understanding of crosstalk-induced noise, glitch propagation, signal electromigration (Signal EM), and managing reconvergent timing paths affected by crosstalk delay
DFT Mode Timing Validation: Define, audit, and validate constraints across multiple operational modes, specifically targeting Scan Shift & Capture, At-Speed Testing, Memory BIST (MBIST), and Logic BIST (LBIST) concurrent execution modes
Cross-Functional Leadership: Collaborate with DFT Engineers to resolve test mode constraints, RTL Designers to fix structural CDC/RDC violations, and P&R Teams to guide placement, clock-tree synthesis (CTS), and routing optimization
Automation & Flow Development: Write advanced, production-grade Tcl scripts for PrimeTime/Tempus environments
Utilize Python or Perl to build regression suites, analyze timing violations, and compare SDC variations
- Your profile
- Qualifications and skills to help you succeed
Bachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or a related field.
Minimum 13+ years of relavent experience in STA full chip
Core Tool Expertise (Mandatory)
Sign-off STA: Synopsys PrimeTime (PT/PT-PX) and Cadence Tempus.
Timing Closure / ECO: Cadence Tempus, Synopsys PrimeTime/PrimeClosure & Tweaker
Constraints Validation: Synopsys TCM/GCA, Ausdia TimeVision, SpyGlass Constraints, or Cadence CCD
Run strict constraints verification using industry-standard tools (Synopsys TCM, SpyGlass Constraints, or Cadence CCD) to eliminate unconstrained paths, incorrect clock-gating checks, and conflicting case analysis settings between functional and DFT model
Hands-on experience reading, writing, and parsing Unified Power Format (UPF) constraints to validate low-power design architectures (e.g., power-gating, isolation cells, retention registers, and level-shifter placement
Familiarity with Logic Equivalency Checking using industry tools like Cadence Conformal LEC or Synopsys Formality to verify that optimization/ECO steps maintain functional equivalence
Deep understanding of advanced node variation models (POCV/LVF), temperature inversion, crosstalk/noise analysis, and hierarchical top-level clock distribution networks
