We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Lead SoC architecture across multiple teams and disciplines, including IP architects, design, verification, validation, firmware, security, power management, software and IP development.
Architect and analyze different aspects, including multi chiplets connectivity, chip partitioning, package/board constraints, chip fabric and how SoC subsystems must support them.
Define top-level SoC structures, detailing interconnects, clock distribution, and power domains to ensure seamless system integration and operational efficiency.
Manage the SoC architecture specification and lead it throughout the entire product life-cycle, concept, modeling, implementation, and silicon bring-up.
Drive architectural analyses exploring different architectural/implementation alternatives, analyze and recommend the optimal solution balancing between performance, features, power, schedule, and cost.
Minimum qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
10 years of experience leading the architectural definition of high-performance SoCs from concept through production.
Experience working and implementing multi-chiplet systems within silicon process technology.
Experience with SoC architecture, including interconnects, memory hierarchies, and system-level reasoning.
Experience writing architecture specifications.
Preferred qualifications
Master’s or PhD in Electrical Engineering or Computer Engineering.
Experience with functional safety (FuSa) and hardware safety mechanisms designed to meet targets (e.g., ASIL).
Experience in defining security architectures, debug infrastructure, and secure boot sequences.
Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
10 years of experience leading the architectural definition of high-performance SoCs from concept through production.
Experience working and implementing multi-chiplet systems within silicon process technology.
Experience with SoC architecture, including interconnects, memory hierarchies, and system-level reasoning.
Experience writing architecture specifications.