You will bridge the gap between ASIC capabilities and core block-storage services to deliver unprecedented Input/Output Operations per Second (IOPS) and latency metrics while guaranteeing end-to-end data integrity and confidentiality.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $174000 - $252000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Develop low-level drivers and kernel-level modules.
Develop embedded C++ services running natively on ARM CPU cores to manage storage queues, ring buffers, and Peripheral Component Interconnect Express (PCIe)/Direct Memory Access (DMA) controllers.
Optimize the data-path for microsecond-level latency and millions of IOPS using advanced hardware features like physical doorbells and direct cache routing.
Minimum qualifications
Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent practical experience.
5 years of software development experience in C or C++ with a focus on systems programming.
Experience with low-level systems architecture: PCIe, DMA, IOMMU, memory-mapped I/O (MMIO), and interrupt handling.
Experience debugging on pre-silicon or early bring-up platforms using hardware emulators (e.g., P3, CSS models) or physical logic analyzers/JTAG.
Preferred qualifications
Master’s degree or PhD in Engineering, Computer Science, or a related technical field.
Experience with custom SoC storage virtualization technologies (e.g., NVMe/SCSI controller emulation, VirtIO).
Familiarity with storage data protection protocols, including block cryptography and data integrity validation (logical block addressing (LBA) mapping, cryptographic hashes).
Understanding of hardware-level security architectures.
Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent practical experience.
5 years of software development experience in C or C++ with a focus on systems programming.
Experience with low-level systems architecture: PCIe, DMA, IOMMU, memory-mapped I/O (MMIO), and interrupt handling.
Experience debugging on pre-silicon or early bring-up platforms using hardware emulators (e.g., P3, CSS models) or physical logic analyzers/JTAG.
