Own microarchitecture and implementation of Internet Protocols (IPs) and subsystems.
Work with Architecture, Firmware, and Software teams to drive feature closure and develop micro-architecture specifications.
Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
Identify and drive power, performance, and area improvements.
Minimum qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
Experience with logic synthesis to improve RTL code, performance, and power. Experience with low-power design
Preferred qualifications
Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture
Experience with coding languages (e.g., Python or Perl).
Experience in System on a Chip (SoC) designs and integration flows.
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Knowledge of high-performance and low-power design techniques.
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
Experience with logic synthesis to improve RTL code, performance, and power. Experience with low-power design