Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
Deliver designs that meet PPA and functional goals with modern techniques, interpret the techniques into design constructs, and languages in order to participate in SoC integration effort.
Work closely with the functional verification team to ensure production quality designs, and with the physical design team to meet frequency, power, and area goals.
Minimum qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in microprocessor architecture.
Experience in high-performance CPU or AI accelerator logic/RTL design/integration including microarchitecture definition and PPA optimizations.
Experience in CPU and cache subsystem integration with SoCs.
Experience with a Hardware Description Language (HDL) and front-end design methodology.
Experience with RTL static checks (e.g., lint and CDC).
Preferred qualifications
Experience with ARM Instruction set architecture.
Experience with SOC design, architect and integration.
Experience with real-time operating systems (e.g. Android).
Experience with DFT, sensor integration, debug architecture.
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in microprocessor architecture.
Experience in high-performance CPU or AI accelerator logic/RTL design/integration including microarchitecture definition and PPA optimizations.
Experience in CPU and cache subsystem integration with SoCs.
Experience with a Hardware Description Language (HDL) and front-end design methodology.
Experience with RTL static checks (e.g., lint and CDC).