US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Manage the handoff of library collateral (e.g., Taiwan Semiconductor Manufacturing Company (TSMC) process design kits (PDKs), Synopsys, and other third-party intellectual properties (IPs)) to projects, performing checks to ensure data integrity.
Drive library validation across views (.lib, .db, .ndm, .lef, .gds) using tools like Siemens Solido Crosscheck (formerly Fractal Crossfire).
Perform Logic Equivalency Checking (LEC) using tools such as Formality or Conformal.
Oversee library updates in ASIC projects, applying methodical processes to detect and prevent errors during releases.
Minimum qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with managing vendor engagements and library delivery schedules in an ASIC design environment.
Preferred qualifications
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in Logic Equivalency Checking (LEC) (e.g., Formality or Conformal).
Experience with library validation tools (e.g., Solido Crosscheck) and understanding of foundation library PDKs from foundries (e.g., TSMC).
Ability to manage ASIC project library updates and releases.
Ability to compile libraries and debug issues across design views (.lib, .db, .ndm, .lef, .gds).
Excellent scripting languages skills such as Tcl or Python to automate workflows and experience creating technology library management and installation flows with integrated validation.
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with managing vendor engagements and library delivery schedules in an ASIC design environment.