We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
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Plan the formal verification strategy, create the properties and constraints for the digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
Resolve difficult to verify properties.
Contribute improvements to methodologies to enhance formal verification results.
Architect and implement reusable formal verification components.
Minimum qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with formal and design verification.
Experience with SystemVerilog or Verilog.
Experience working with one or more formal verification tools (e.g., Jasper, VC Formal, Questa Formal, 360-DV).
Preferred qualifications
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
6 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based Integrated Circuits (ICs) and chips.
Experience with scripting languages.
Excellent communication and collaboration skills.
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with formal and design verification.
Experience with SystemVerilog or Verilog.
Experience working with one or more formal verification tools (e.g., Jasper, VC Formal, Questa Formal, 360-DV).