## Grow with us
About this opportunity
- Silicon Front-End CAD DV Engineer – Dual-Vendor Flows, Methodology & AI
- Austin, Texas. This is not a remote work opportunity
Shape how Ericsson’s ASICs and FPGAs are verified, from IP testbench to SoC regression. Combine deep SystemVerilog and UVM expertise with software engineering and practical AI to build faster, more reliable verification flows across silicon programs. Work on ASIC and FPGA programs for Ericsson’s 5G and 6G portfolio at advanced nodes, including Intel 18A and TSMC 3/2nm. Drive measurable gains in verification quality, coverage closure, and regression turnaround through reusable testbench architecture, qualified DV flows, and AI-driven automation.
Ericsson Silicon develops ASICs and FPGAs for telecommunications infrastructure. We are seeking a hands-on engineer to advance our front-end verification methodology, DV flows, and infrastructure—not simply support existing tools. You will join a global methodology team spanning Austin, Stockholm, Lund, and India, working across verification methodology, EDA flow support, and OneRun, our front-end flow orchestration platform. Partner with IP and SoC verification teams, design and back-end methodology owners, and EDA vendors. Own qualified engineering solutions in your area; partner with the Silicon CAD Technical Program Manager on delivery and adoption. Project verification leads retain signoff approval. What you will do Architect scalable DV environments: Build layered, reusable SystemVerilog/UVM testbenches with clean separation, automated regression, and clear documentation. An early deliverable is a maintainable testbench for our register generation tool. Develop high-quality VIP: Create efficient, reusable UVM verification IP with strong protocol checking, coverage, and low simulation overhead, independent of any single vendor’s VIP library. Advance verification methodology: Develop IP-to-SoC methodology across constrained-random and directed simulation, assertions, formal, and coverage closure. Keep environments portable across Cadence and Synopsys simulation and formal tools. Apply AI to DV engineering: Use and improve AI tools such as ChipAgents and Kiro for testbench creation, spec-driven development, debug, and regression triage. Validate benefits against reproducible baselines; retain engineering review. Deliver production-ready capabilities: Automate regression and release qualification in Jenkins CI and OneRun. Run representative pilots on real designs and support controlled rollout without disrupting active tapeout schedules. Multiply technical impact: Resolve complex flow and tool issues, influence EDA vendor improvements, and mentor engineers through design reviews, documentation, and shared ownership.
Show the full description
## Join our Team
What you will bring
- 5+ years in ASIC/FPGA design verification or DV methodology, with evidence of production deployment and successful tapeout contributions.
- Deep hands-on expertise in SystemVerilog and UVM testbench architecture at IP, subsystem, and SoC level, including constrained-random verification, SVA, and functional and code coverage closure.
- Strong experience with Cadence Xcelium and/or Synopsys VCS, and formal or lint/CDC tools. Specialist depth in one domain is valued; expertise in every domain is not required.
- Strong Python and scripting skills, with experience building maintainable automation using Linux, version control, code review, CI, automated tests, and controlled releases.
- Demonstrated ability to turn difficult verification problems into reusable solutions across projects, explain technical trade-offs, and collaborate effectively in distributed teams.
- A bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field—or equivalent practical experience.
Critical Exposure
Practical application of AI/ML or LLM-based tools to testbench generation, coverage prediction, or failure triage; register-model development (UVM RAL, SystemRDL, IP-XACT); migrating verification environments between EDA vendors; or measurable improvements in coverage closure time and regression cost.
Own the engineering behind the verification flow—not just a step within it. Influence methodology, work directly with IP and SoC teams and EDA vendors, and turn new DV and AI ideas into production capabilities. Your impact will be measured in higher silicon quality, faster coverage closure, and verification environments that engineers trust across programs.
