Cisco
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You will work with Cisco's best-in-class Silicon Photonics team.
Meet the Team
Cisco’s Silicon One Optics Group (S1O) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of innovative IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping S1O’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry.
You will work with Cisco's best-in-class Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures.
Your Impact
We are seeking an experienced Physical Design Technical Leader to guide our engineering team and drive physical implementation for Cisco's next-generation silicon photonics driver and receiver ICs, powering 100G, 200G, and 400G-per-lambda Co-Packaged Optics (CPO) and optical engine solutions. In this high-impact role, you will lead the physical design strategy and execution for high-performance silicon integrating sophisticated digital control logic, CPU subsystems, high-speed standard interfaces (UCIe), and ultra-fast transmit/receive data-paths in groundbreaking process nodes (TSMC sub-5nm/3nm/2nm).
As a Technical Leader, you will own block-level and full-chip physical implementation from synthesis through final tape-out (TO) while advising, mentoring, and scaling a team of physical design engineers. You will establish advanced physical design methodologies, drive floor-planning, place & route, low-skew clock and power distribution, multi-corner timing closure (STA), EM/IR integrity, and DRC/LVS physical verification sign-off. Additionally, you will partner closely with Architecture, Analog Front-End, Layout, and Photonic packaging teams to ensure first-pass silicon success and drive breakthrough execution across the complete product lifecycle from concept to production.
Technical & People Leadership: Lead, mentor, and technically steer a team of physical design engineers, driving task allocations, schedule tracking, and design reviews.
Full-Flow Ownership: Own full-chip and hierarchical block-level RTL-to-GDSII implementation and sign-off on advanced nodes.
Methodology & Flow Innovation: Architect robust, automated backend flows (Innovus / Fusion Compiler, Pegasus / Calibre, Voltus / RedHawk) to boost team productivity and tapeout predictability.
Multi-functional Collaboration: Serve as the primary physical design communicate with Analog Design, Custom Layout, Package Co-Design, and Foundry partners.
Bachelor’s degree or equivalent experience in electrical engineering, Electronics & Communication or related field with minimum 12+ years of Industry experience
8+ years of physical design (PD) experience delivering ASIC/SoC designs in sophisticated CMOS technology nodes (7nm/5nm/3nm/2nm)
Proven experience driving the full RTL-to-GDSII flow at block and/or full-chip level-including hierarchical floor-planning, power grid design, place & route (P&R), clock tree synthesis (CTS), timing closure, and physical verification sign-off.
Strong proficiency with industry-standard EDA tools (Innovus/ICC2/Fusion, Tempus/PrimeTime, Voltus/RedHawk, Calibre/Pegasus etc.)
Strong scripting proficiency in Tcl, Python, Bash, or Perl for flow automation, quality of results (QoR) tracking, and efficiency improvements
Ability to lead a team of PD engineers & work collaboratively with globally dispersed multi-functional teams
Education: Master's degree (M.S. / M.Tech) in Electrical Engineering, VLSI Design, or Microelectronics.
Experience: 12-15+ years of ASIC/SoC physical implementation experience with multiple successful tape-outs in ground-breaking process nodes (sub-5nm, 3nm, or 2nm GAA/nanosheet).
Technical Team Leadership: Consistent record of leading physical design project execution, defining schedules, conducting design reviews, and driving tapeout readiness for a team of PD engineers.
Mixed-Signal & High-Speed IP Integration: Strong experience handling floorplanning and noise isolation for sensitive mixed-signal macros, high-speed SerDes, Die-to-Die (D2D / UCIe) interfaces, CPU subsystems, and 2.5D/3D packaging environments.
Front-End / Equivalence Flows: Familiarity with logic synthesis (Cadence Genus / Synopsys Design Compiler) and formal equivalence checking (Cadence LEC / Synopsys Formality).
Post-Silicon Correlation: Experience supporting silicon bring-up and correlating pre-silicon timing/power models with post-silicon lab measurements.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Disclaimer
To ensure that we hire the best talent in the right way, we follow a strict hiring process and recently, Cisco has been made aware of fraudulent recruiters claiming to be from the company. Please be advised that any communication from Cisco about careers will:
be in direct response to an application you have submitted through the company career site
begin with screening or an interview
originate from a Cisco email address, and
be conducted across email, phone, or WebEx
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If you are the target of a recruiting scam, consider filing a report with your local law enforcement authorities. Cisco bears no responsibility, and cannot be held liable, for any claims, damages, expenses, or other inconvenience resulting from or in any way connected to recruiting scams.
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