Responsibilities Include
Designing UVM/SystemVerilog testbenches.
Defining new DV methodologies.
Enhancing existing testbenches.
End-to-end verification of various design blocks.
Contributing to top level verification.
Be a part of emulation testing efforts.
Participate in the ASIC bring-up
Education and Experience Required
Bachelor’s or master’s degree in EE and CE.
3+ years of ASIC Design Verification
Knowledge and Skills
Collaborative and team-focused, with the drive to learn and grow
Hands-on experience on System Verilog and UVM methodology
Ability to construct testbench including scoreboard, agents, sequencers, and monitors
Ability to debug issues independently
Good Scripting experience (Python, Perl, TCL, shell programming) is a plus
Proficient in constrained random DV environments
Good written and verbal communication skills
Knowledge on latest high speed Ethernet protocol and packets is a plus.
We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.