Participate in the complete RTL development lifecycle, from architecture and microarchitecture definition to implementation and verification
Optimize RTL designs for timing, latency, resource utilization, and power efficiency
Perform logic synthesis, timing analysis, and optimization to meet design constraints
Collaborate with verification engineers to ensure functional correctness and comprehensive test coverage
Analyze system-level and software requirements and implement appropriate hardware-software interfaces
Integrate proprietary digital IP into complex FPGA/ASIC architectures
Participate in design reviews, debugging, and continuous improvement of engineering processes
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline, or equivalent practical experience
4+ years of professional experience in FPGA or ASIC digital logic design
Strong practical experience in RTL development using SystemVerilog (mandatory)
Solid understanding of digital logic design, computer architecture, and RTL microarchitecture
Experience with logic synthesis, static timing analysis (STA), and timing optimization
Practical experience with FPGA or ASIC design and implementation workflows
Understanding of clock-domain crossing (CDC), synchronous digital design, and hardware interfaces
Experience with simulation-based RTL verification and debugging
Strong analytical, problem-solving, and communication skills
English proficiency sufficient for effective collaboration within an international engineering team
Desirable
Experience with AMD/Xilinx FPGA platforms, particularly AMD Versal
Experience with AMD Vivado and related FPGA implementation tools
Familiarity with Synopsys VCS, Siemens Questa, or equivalent simulation tools
Experience with digital signal processing (DSP), waveform generation, or high-speed data acquisition
Experience developing deterministic, ultra-low-latency digital systems
Familiarity with AXI, PCIe, DDR, or other high-performance hardware interfaces
Experience with ASIC-oriented RTL development and reusable digital IP
Knowledge of Python, Tcl, or other languages used for development automation
Experience with hardware-software co-design and embedded systems
Experience in quantum computing, telecommunications, measurement equipment, or other performance-critical digital systems
What’s in it for you?
Strong community: Work alongside top professionals in a friendly, open-door culture that values initiative and empowers its people to succeed
Fast-paced & agile environment: Be part of a dynamic, fast-moving organization that champions efficiency and innovation
Global exposure: Collaborate with international, cross-functional teams and contribute to large-scale initiatives
Tailored learning: Boost your skills with internal events (meetups, conferences, workshops), Udemy access, language courses, and company-paid certifications
Flexibility: Balance office and remote work to fit your rhythm
Care: Take advantage of our extensive benefits offering, aligned with the best market standards
The salary starts from 3000 Eur gross. The final salary depends on the previous experience and professional knowledge of the candidate.
About us
At Ciklum, we are always exploring innovations, empowering each other to achieve more, and engineering solutions that matter. With us, you’ll work with cutting-edge technologies, contribute to impactful projects, and be part of a One Team culture that values collaboration and progress.
Our Slovakia hub brings together passionate professionals working on global initiatives. Be part of a close-knit team that’s driving digital transformation and creating lasting impact.
Explore, empower, engineer with Ciklum!
Interested already? We would love to get to know you! Submit your application. We can’t wait to see you at Ciklum.
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