Support timing signoff for pre-layout and post-layout stages.
Perform cross-functional reviews for timing convergence and provide recommendations.
Generate timing reports and communicate closure status to project stakeholders.
Minimum Qualifications
15+ years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs.
Strong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow.
Hands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.
Good understanding of clock tree, clock uncertainty, latency, skew, and jitter.
Expertise in timing constraints development and debugging.
Strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis.
Experience with timing closure techniques and ECO methodologies.
Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus.
Good scripting skills in Tcl, Perl, or Python. Exposure to automation and flow development.
Ability to analyze and resolve timing violations independently.
Experience in low-power timing analysis and UPF/CPF-aware STA.
Expertise with SI-aware timing, Crosstalk analysis, and IR-drop-aware timing closure.
Good knowledge of advanced technology nodes and variation-aware signoff methodologies.
Experience in collaborating cross-functionally with PD, RTL, and Signoff teams.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
