Department expertise spans requirements development, architecture activities, RTL design, ASIC development, FPGA implementation, timing analysis, verification collaboration, integration support, and system-level troubleshooting.
Engineers have opportunities to broaden across conceptual architecture, requirements development, HDL ownership, FPGA implementation, timing analysis, verification collaboration, subsystem development, and integration activities while deepening selected technical specialties over time. The organization intentionally supports growth from focused contributors toward broader technical ownership, subsystem responsibilities, mentorship, and technical leadership roles as experience develops.
Teams are intentionally composed of engineers with complementary strengths spanning architecture, implementation, verification, integration, timing, and troubleshooting. The role is not intended to imply that every engineer must simultaneously be an expert in all disciplines.
Responsibilities
Support ASIC, FPGA, or mixed ASIC/FPGA developments depending on assignment
Contribute to requirements development, refinement, interface definition, conceptual architecture activities, and traceability efforts appropriate to role level
Develop HDL / RTL for ASIC, FPGA, and SoC systems
Compile, simulate, debug, and troubleshoot digital designs
Perform and/or support synthesis, implementation, constraints development, timing closure, and tool execution activities
Collaborate with verification teams to support simulation, debug, coverage, and integration goals
Apply timing concepts, CDC fundamentals, and integration considerations
Support broader system troubleshooting and integration activities
Communicate technical status, risks, dependencies, and tradeoffs proactively
Behavioral Expectations
Operate with ownership appropriate to role level
Independently manage assigned scope and execution
Develop technical breadth while deepening selected expertise
Support peer development and technical collaboration
Build systems awareness beyond immediate design boundaries
Contribute to technical leadership activities appropriate to level
Associate, Level 2
Independently manage assigned technical scope and execution responsibilities
Rapidly develop RTL, simulation, debug, timing, implementation, and integration skills while building broader systems awareness
Participate in requirements refinement, traceability, and integration activities appropriate to experience level
Experienced, Level 3
Own blocks or functional areas
Contribute to requirements development, interface definition, implementation support, and technical closure
Support integration and cross-functional troubleshooting activities
Lead teams, subsystem efforts, and cross-functional initiatives
This position is expected to be 100% onsite. The selected candidate will be required to work onsite at one of the listed locations.
Basic Qualifications (Required Skills/Experience)
This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.
Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
Bachelor’s degree and 2+ years of experience with years FPGA, ASIC, or SoC digital design; or a BS and completed MS degree
Experience with HDL development, simulation, debug, and synthesis
Strong digital design fundamentals (coursework in digital logic design, computer architecture, ASIC design flow, VLSI Design, etc.)
Experience troubleshooting digital systems (debugging RTL design, HDL/architecture)
Preferred Qualifications (Desired Skills/Experience)
Experienced, Level 3: 5+ years of related engineering experience
Bachelor’s Degree or Master's Degree in EE, Computer Engineering/Science, or related field
Active U.S. Secret Security Clearance
Requirements development and traceability experience
FPGA implementation including constraints and timing closure
Static timing analysis experience
Understanding of timing fundamentals and CDC concepts
Verification collaboration experience
High-speed interfaces, processor integration, memory subsystems, or SoC integration
Mentoring or technical leadership exposure
Familiarity with industry-standard tools and methodologies
Conflict of Interest
Successful candidate for this job must satisfy the Company’s Conflict of Interest (COI) assessment process.
Typical Education/Experience
Associate, Level 2: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 2 or more years' related work experience or an equivalent combination of technical education and experience (e.g. Master). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Experienced, Level 3: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Relocation
This position offers relocation based on candidate eligibility. Note: Basic relocation will be offered for eligible internal candidates.
Drug Free Workplace
Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.
Shift Work
This position is for 1st shift.
Total Rewards
At Boeing, we strive to deliver a Total Rewards package that will attract, engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.
The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work.
The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location, date of hire, and the applicability of collective bargaining agreements.
Pay is based upon candidate experience and qualifications, as well as market and business considerations.
Summary pay range for Associate, (Level 2): $98,600 - $133,400
Summary pay range for Experienced, (Level 3): $119,850 - $162,150
Language Requirements
Not Applicable
Education
Bachelor's Degree or Equivalent
Relocation
This position offers relocation based on candidate eligibility.
Export Control Requirement
Safety Sensitive
Security Clearance
This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret Clearance Post-Start is required.
Visa Sponsorship
Employer will not sponsor applicants for employment visa status.
- Contingent Upon Award Program
- This position is not contingent upon program award
Shift
Shift 1 (United States of America)
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