Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
Work with RTL designers to troubleshoot and resolve design issues.
Drive verification strategy and methodology for SoCs in server and networking applications.
Required Qualifications
Bachelor’s degree in Electrical Engineering (Master’s preferred).
8+ years of experience in SoC verification, particularly for server and networking applications.
Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
Proficiency with industry-standard simulators, version control, and regression systems.
Strong debugging and coverage analysis skills.
Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
Familiarity with verification of switching architectures, including packet processing and forwarding engines.
Excellent communication skills and ability to work independently with minimal supervision.
Preferred Qualifications
Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
Knowledge of Ethernet/PCIe switching and central buffer architectures.
Experience with emulation platforms and hardware-software co-verification
Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.