Develop user-controlled random constraints in transaction-based verification methodologies.
Write assertions, cover properties, and analyze coverage data.
Create VIP abstraction layers for sequences to simplify and scale verification deployments.
Basic Qualifications
Minimum of 12 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications.
Strong academic and technical background in Electrical Engineering or Computer Engineering (bachelor’s degree required, master’s preferred).
Professional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance.
Knowledge of industry-standard simulators, revision control systems, and regression systems.
Entrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction.
Required Experience
Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments.
Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above.
Ability to independently develop test plans and sequences in UVM to generate stimuli.
Experience writing assertions, cover properties, and analyzing coverage data.
Developing VIP abstraction layers for sequences to simplify and scale verification deployments.
Preferred Experience
Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC.
Experience with buffering and queuing with QoS on complex NOC-based SoCs.
Analyzing performance at the system level on switching fabrics.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
