Basic Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
15+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
5+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
Strong scripting ability in Tcl, Python, and/or Perl.
Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
Required Experience
Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
Experience with Cadence and/or Synopsys physical design tools/flows.
Preferred Experience/Nice to Have
Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
Track record of building and scaling physical design teams through multiple tapeouts.
Knowledge of agentic AI solutions for EDA automation.
Base salary range is CAD 200,000 to CAD 250,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
