Key Responsibilities
Physical Implementation: Contribute to the RTL-to-GDSII flow — floorplanning, power planning, placement, clock tree synthesis (CTS), and routing — with guidance from senior engineers
Static Timing Analysis: Run STA across PVT corners in multi-corner multi-mode (MCMM) setups and help resolve setup/hold violations with the design and layout teams
Power Integrity: Support power delivery network (PDN) work, including IR-drop and electromigration (EM) analysis
Physical Verification: Run DRC, LVS, antenna, and ERC checks and drive issues to clean signoff
Mixed-Signal Integration: Work with analog layout engineers on floorplan co-optimization and constraints at sensitive analog/digital boundaries
DFT: Support scan chain stitching and ATPG pattern generation
Flow and Automation: Script and automate repetitive physical design tasks to improve the team's flow
Silicon Support: Support silicon bring-up and debug, correlating physical design decisions with lab measurements
Requirements / Must Have Skills
Digital Design Fundamentals: Solid understanding of digital logic, CMOS basics, and the IC design flow
Timing Concepts: Working understanding of static timing analysis, setup/hold, and clock domain crossing (CDC)
EDA Exposure: Coursework, internship, or tape-out project experience with digital implementation tools (Cadence Genus/Innovus/Tempus or an equivalent flow)
Scripting: Ability to write Tcl, Python, or shell scripts to automate repetitive tasks
Engineering Rigor: Careful, methodical approach to closure — able to track many small violations to zero without losing any
Teamwork and English: Strong collaboration with design and layout teams, and sufficient English for daily communication and technical documents
Preferred Education and Experience
Master's degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field
Tape-out experience from a university project or internship is a strong plus
Exposure to power analysis (IR-drop, EM) or power intent specification (UPF/CPF) is a plus
Exposure to DFT methodologies (scan insertion, compression, ATPG, JTAG/boundary scan) is a plus
Familiarity with both mature analog process nodes (e.g., 180nm BCD) and advanced digital nodes is a plus
Experience using AI tools to improve flow development or engineering productivity is a plus
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
Job Req Type: Graduate Job
Required Travel: No
