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About the Role
We are seeking a motivated and detail-oriented Design Verification Intern to join our CSS DV team. You will work alongside experienced design and verification engineers to validate IP and subsystem-level designs for high-performance semiconductor products in consumer markets.
This role offers hands-on experience with System Verilog based verification, simulation environments, testbench development, and functional coverage Ideal for students or early-career engineers exploring a path into ASIC/SoC development.
Key Responsibilities
Assist in developing and executing verification plans for digital IP blocks and subsystems.
Develop, enhance, and maintain testbench components using System Verilog, UVM, or similar methodologies.
Run simulations, analyze results, identify failures, and help debug issues.
Create directed and constrained-random tests to validate functionality and corner cases.
Perform functional, code, and assertion coverage reporting, review, and tracking.
Work closely with design and architecture teams to clarify specifications and ensure coverage completeness.
Support automation flows and continuous regression infrastructure with scripting.
Document verification environments, methodologies, and results.
Required Skills & Qualifications
Pursuing a Bachelor’s / Master’s / PhD in Electrical Engineering, Computer Engineering, or a related discipline.
Strong understanding of digital logic design and computer architecture.
Coursework or practical exposure to
Verilog/System Verilog or VHDL
RTL design principles
Simulation workflows
Familiarity with scripting languages (Python, Perl, Tcl, Bash, etc.).
Good analytical and debugging skills.
Strong communication and willingness to learn in a fast-paced engineering environment.
Nice-to-Have Skills
Experience with UVM-based verification.
Familiarity with EDA tools (Xcelium, etc.).
Knowledge of
SoC design concepts
Bus protocols (AXI, AHB, APB)
Assertions (SVA)
Coverage-driven verification
What You Will Learn
Industry-standard ASIC/SoC verification methodologies.
Writing and debugging System Verilog-UVM testbench components.
Simulation and coverage-driven verification flows.
Collaboration with digital design, architecture, and modelling teams.
Why Join Us
Gain hands-on verification experience with real silicon IP.
Work with experienced engineers who provide mentorship and guidance.
Exposure to modern EDA tools and methodologies.
Opportunity to convert to full-time/graduate roles.
Collaborative, learning-driven workplace culture.
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
Job Req Type: Internship/Cooperative
Required Travel: No
