AMD
From AMD's careers page
Status: listed on the employer's own careers page when we last checked (daily). Confirm on their site before applying.
MTS Timing constraint development ENGINEER THE ROLE: The focus of this role is to plan and develop the Timing constraints of IPs Subsystem or Full chip.
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
MTS Timing constraint development ENGINEER
The focus of this role is to plan and develop the Timing constraints of IPs Subsystem or Full chip. This involves ownership of SDC development, SDC generation, verification, promotion/demotion and equivalence checking. The role might also epxand to (if needed) synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on technical issues.
Main responsibility is to own constratins, SDC developement for IPs, SS and SoCs. Including SDC generation, verification, promotion, demotion and equivalence using third party or self built tools.
Prior experience with Lint, CDC and RTL & Netlist based static checks is a plus
Collaborate with designer and PNR teams to achieve closure.
Understand duration required, plan and execute as per schedule.
Complete quality delivery for synthesis and timing closure.
Debug and resolve technical issues
Existing SDC, constraints development with or without using fisthail, excellicon or TCM.
Experienced in synthesis, LEC, CLP and timing closure
Preferred top level or SOC level experience
Have handled blocks with complex designs, high frequency clocks and complex clocking
complete understanding of timing constraints, low power aspects and concepts of DFT
Have debug experience to solve issues.
Interst in AI, Scripting and automation
Bachelors with 7 years of experience or Masters degree with 5 years of experience in Electrical Engineering
#LI-AB1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
MTS Timing constraint development ENGINEER
The focus of this role is to plan and develop the Timing constraints of IPs Subsystem or Full chip. This involves ownership of SDC development, SDC generation, verification, promotion/demotion and equivalence checking. The role might also epxand to (if needed) synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on technical issues.
Main responsibility is to own constratins, SDC developement for IPs, SS and SoCs. Including SDC generation, verification, promotion, demotion and equivalence using third party or self built tools.
Prior experience with Lint, CDC and RTL & Netlist based static checks is a plus
Collaborate with designer and PNR teams to achieve closure.
Understand duration required, plan and execute as per schedule.
Complete quality delivery for synthesis and timing closure.
Debug and resolve technical issues
Existing SDC, constraints development with or without using fisthail, excellicon or TCM.
Experienced in synthesis, LEC, CLP and timing closure
Preferred top level or SOC level experience
Have handled blocks with complex designs, high frequency clocks and complex clocking
complete understanding of timing constraints, low power aspects and concepts of DFT
Have debug experience to solve issues.
Interst in AI, Scripting and automation
Bachelors with 7 years of experience or Masters degree with 5 years of experience in Electrical Engineering
#LI-AB1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
A free account lets you apply, save this job, see how well you match and check your resume against it.
Scores your resume against this job the way resume scanners do: the job's hard and soft skills, searchability, recruiter tips and formatting.
Create a free account to see your score. Your resume stays in this browser until then, and we never store it.
Already a member? Sign in