AMD
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ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
Own full-chip static timing analysis (STA) and timing closure for complex SoC designs, from
early design netlist through final signoff. Partner closely with PnR, synthesis/DFT, and CAD
teams to drive timing convergence, methodology improvements, and flow automation across the
business unit.
Timing Closure & Signoff
Own full-chip timing closure across setup, hold, and DRV (transition/capacitance/noise) signoff
Drive multi-corner/multi-mode (MMMC) timing convergence across PVT corners and modes
Analyze and resolve SI/crosstalk, OCV/POCV, and clock-related (skew, jitter, uncertainty) impacts on timing
Perform root-cause analysis of timing violations and drive fixes through ECO, PnR trials etc.
Generate, validate, and hand off ECOs to PnR PD teams; verify legalization and post-ECO QoR
Clock Architecture
Guide clock tree build strategy across multiple methodologies (H-tree, MSCTS/multi-source CTS, clock mesh)
Define clock structure and skew/latency targets in partnership with clock architecture and PD teams
Cross-Team Collaboration
Work with PnR engineers to drive timing convergence at each implementation stage (place, CTS, route, ECO)
Provide SDC (constraint) analysis, quality review, and feedback to design and synthesis teams
Feed back repeater/floorplan/design guidance across SoC based on timing analysis
Analyze run data and provide actionable feedback to PD execution teams
Collaborate across business units, CAD, and central methodology teams to define and drive requirements
Interface with other PPA (or equivalent) teams internal to AMD on cross-cutting timing topics
Methodology & Automation
Define and drive common STA methodology and signoff criteria across the business unit
Build automation to streamline design signoff checks, QoR tracking, and dashboard generation
Identify and adopt best practices from across AMD and industry to continuously improve flow/project best practices
Drive stage-by-stage improvements in competitiveness (PPA, turnaround time) of the AMD design flow
Communication
Organize and present complex technical timing data clearly and concisely to technical and management audiences
Document methodology, flows, and known issues for broader team consumption
BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field
Full chip timing experience preferred
Markham, ON
#LI-JE1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Own full-chip static timing analysis (STA) and timing closure for complex SoC designs, from
early design netlist through final signoff. Partner closely with PnR, synthesis/DFT, and CAD
teams to drive timing convergence, methodology improvements, and flow automation across the
business unit.
Timing Closure & Signoff
Own full-chip timing closure across setup, hold, and DRV (transition/capacitance/noise) signoff
Drive multi-corner/multi-mode (MMMC) timing convergence across PVT corners and modes
Analyze and resolve SI/crosstalk, OCV/POCV, and clock-related (skew, jitter, uncertainty) impacts on timing
Perform root-cause analysis of timing violations and drive fixes through ECO, PnR trials etc.
Generate, validate, and hand off ECOs to PnR PD teams; verify legalization and post-ECO QoR
Clock Architecture
Guide clock tree build strategy across multiple methodologies (H-tree, MSCTS/multi-source CTS, clock mesh)
Define clock structure and skew/latency targets in partnership with clock architecture and PD teams
Cross-Team Collaboration
Work with PnR engineers to drive timing convergence at each implementation stage (place, CTS, route, ECO)
Provide SDC (constraint) analysis, quality review, and feedback to design and synthesis teams
Feed back repeater/floorplan/design guidance across SoC based on timing analysis
Analyze run data and provide actionable feedback to PD execution teams
Collaborate across business units, CAD, and central methodology teams to define and drive requirements
Interface with other PPA (or equivalent) teams internal to AMD on cross-cutting timing topics
Methodology & Automation
Define and drive common STA methodology and signoff criteria across the business unit
Build automation to streamline design signoff checks, QoR tracking, and dashboard generation
Identify and adopt best practices from across AMD and industry to continuously improve flow/project best practices
Drive stage-by-stage improvements in competitiveness (PPA, turnaround time) of the AMD design flow
Communication
Organize and present complex technical timing data clearly and concisely to technical and management audiences
Document methodology, flows, and known issues for broader team consumption
BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field
Full chip timing experience preferred
Markham, ON
#LI-JE1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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Hi [Name], I just applied for the Static Timing Analysis / Full Chip Timing Engineer role at AMD. My background in [your most relevant experience] lines up well with what the team is looking for. Would you be open to a quick chat, or could you point me to the right person on the team? Thank you!
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