AMD
From AMD's careers page
Status: listed on the employer's own careers page when we last checked (daily). Confirm on their site before applying.
THE ROLE: This is an outstanding opportunity for an experienced engineer passionate about digital signal processing (DSP) algorithms and their application in high-speed SerDes (Serializer/Deserializer) systems.
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
This is an outstanding opportunity for an experienced engineer passionate about digital signal processing (DSP) algorithms and their application in high-speed SerDes (Serializer/Deserializer) systems. As part of a team, you will optimize and implement advanced DSP algorithms and circuits for 200+Gbps SerDes, with a strong focus on power efficiency and optimization. Your work will directly impact the performance and robustness of AMD’s next-generation connectivity solutions for markets such as data center networking, wireless telecommunications, and aerospace/defense.
Collaborate with architects, hardware engineers, and verification engineers to implement and refine new DSP features for cutting-edge and next-generation SerDes transceivers
Implement DSP algorithms for equalization, filtering and sequence detection
RTL development using front-end ASIC tools (lint, synthesis, STA) to ensure the highest quality code
Develop comprehensive documentation detailing DSP algorithm interactions with SerDes hardware and software components
Strong background and experience in digital design techniques including clock domain crossing, RTL (preferably SystemVerilog), and ASIC front-end design tools and flows
Understanding of power analysis and power reduction techniques for optimization of digital circuitry
Experience in DSP algorithm development and implementation for SerDes, wireless communications or high-speed serial interfaces (Ethernet, PCIe, etc.)
Experience of simulation and modeling of DSP algorithms
Edinburgh, United Kingdom (Hybrid)
#LI-ME
#LI-ONSITE
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
This is an outstanding opportunity for an experienced engineer passionate about digital signal processing (DSP) algorithms and their application in high-speed SerDes (Serializer/Deserializer) systems. As part of a team, you will optimize and implement advanced DSP algorithms and circuits for 200+Gbps SerDes, with a strong focus on power efficiency and optimization. Your work will directly impact the performance and robustness of AMD’s next-generation connectivity solutions for markets such as data center networking, wireless telecommunications, and aerospace/defense.
Collaborate with architects, hardware engineers, and verification engineers to implement and refine new DSP features for cutting-edge and next-generation SerDes transceivers
Implement DSP algorithms for equalization, filtering and sequence detection
RTL development using front-end ASIC tools (lint, synthesis, STA) to ensure the highest quality code
Develop comprehensive documentation detailing DSP algorithm interactions with SerDes hardware and software components
Strong background and experience in digital design techniques including clock domain crossing, RTL (preferably SystemVerilog), and ASIC front-end design tools and flows
Understanding of power analysis and power reduction techniques for optimization of digital circuitry
Experience in DSP algorithm development and implementation for SerDes, wireless communications or high-speed serial interfaces (Ethernet, PCIe, etc.)
Experience of simulation and modeling of DSP algorithms
Edinburgh, United Kingdom (Hybrid)
#LI-ME
#LI-ONSITE
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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