Own DFT execution from architecture and requirements definition through RTL implementation, verification, physical implementation support, pattern generation, and silicon bring-up.
Partner closely with DFT Architecture and IP/SoC Design teams to define requirements and drive successful DFT implementation across complex SoCs.
Drive correct-by-construction DFT methodologies, design quality, verification completeness, and predictable execution.
Work closely with RTL Design, Verification, Physical Design, STA, and Test Engineering teams to resolve complex design, timing, implementation, and testability challenges.
Lead technical reviews and provide guidance on DFT architecture, methodologies, implementation, verification, and debug.
Drive execution planning, resource prioritization, risk identification, and timely closure of technical dependencies and program deliverables.
Develop and improve DFT methodologies, automation, flows, and infrastructure to improve engineering productivity and design quality.
Provide hands-on technical guidance for complex ATPG, scan, MBIST, timing, simulation, and silicon-debug issues.
Build and develop engineering talent through mentoring, technical guidance, and capability development.
Collaborate effectively with geographically distributed engineering teams and stakeholders.
PREFERRED EXPERIENCE
Extensive experience in ASIC/SoC DFT architecture, design, integration, verification, and implementation.
Strong experience leading end-to-end DFT execution for complex, high-performance SoCs.
Demonstrated experience leading and mentoring DFT engineers and driving technical execution across multiple projects/programs.
Deep understanding of Scan insertion, ATPG, compression, MBIST, Boundary Scan/JTAG, test modes and test architecture.
Strong experience with industry-standard DFT and implementation tools such as Siemens Tessent, Synopsys Design Compiler and SpyGlass or equivalent tools.
Experience defining and developing scalable DFT flows and methodologies.
Strong knowledge of RTL development and integration using Verilog/SystemVerilog.
Experience integrating multiple IPs and DFT structures into large and complex SoCs.
Good understanding of synthesis, simulation, CDC, lint, RTL quality checks, and design verification methodologies.
Strong understanding of Static Timing Analysis, DFT timing constraints and timing closure.
Experience in Scan/ATPG pattern generation, test-flow development, debug, coverage analysis, and characterization.
Excellent hands-on debugging skills with the ability to drive complex technical issues to closure.
Strong scripting and automation experience using Perl, Python and TCL.
Understanding of low-power design concepts including clock gating and power gating.
Experience with post-silicon bring-up and silicon DFT/debug is highly desirable.
Strong communication, stakeholder-management, and organizational skills with the ability to work effectively across global engineering teams.
Proven ability to balance technical depth, people leadership, program execution, and strategic priorities.
ACADEMIC CREDENTIALS
B.E./B.Tech./M.E./M.Tech. in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
Typically 15+ years of relevant semiconductor/SoC design experience, with significant experience in DFT and technical/team leadership.
#LI-RR1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Senior Manager, DFT
THE ROLE
As a Senior Manager – DFT Design within the S3 SoC DFT Team, the successful candidate will provide technical and people leadership for the DFT organization responsible for the architecture, design, integration, verification, and silicon enablement of advanced DFT solutions across complex SoCs.
The candidate will lead a team of DFT engineers and work closely with DFT Architecture, RTL Design, Verification, Physical Design, STA, Test, and Post-Silicon teams to drive robust and scalable DFT solutions across multiple programs.
This role requires a strong combination of deep DFT technical expertise, team leadership, execution ownership, and cross-functional collaboration.
KEY RESPONSIBILITIES
Lead and manage a team of DFT engineers responsible for end-to-end DFT design, integration, verification, and implementation.
Provide technical leadership for complex DFT architectures including Scan, ATPG, MBIST, Boundary Scan/JTAG and related test methodologies.
Own DFT execution from architecture and requirements definition through RTL implementation, verification, physical implementation support, pattern generation, and silicon bring-up.
Partner closely with DFT Architecture and IP/SoC Design teams to define requirements and drive successful DFT implementation across complex SoCs.
Drive correct-by-construction DFT methodologies, design quality, verification completeness, and predictable execution.
Work closely with RTL Design, Verification, Physical Design, STA, and Test Engineering teams to resolve complex design, timing, implementation, and testability challenges.
Lead technical reviews and provide guidance on DFT architecture, methodologies, implementation, verification, and debug.
Drive execution planning, resource prioritization, risk identification, and timely closure of technical dependencies and program deliverables.
Develop and improve DFT methodologies, automation, flows, and infrastructure to improve engineering productivity and design quality.
Provide hands-on technical guidance for complex ATPG, scan, MBIST, timing, simulation, and silicon-debug issues.
Build and develop engineering talent through mentoring, technical guidance, and capability development.
Collaborate effectively with geographically distributed engineering teams and stakeholders.
PREFERRED EXPERIENCE
Extensive experience in ASIC/SoC DFT architecture, design, integration, verification, and implementation.
Strong experience leading end-to-end DFT execution for complex, high-performance SoCs.
Demonstrated experience leading and mentoring DFT engineers and driving technical execution across multiple projects/programs.
Deep understanding of Scan insertion, ATPG, compression, MBIST, Boundary Scan/JTAG, test modes and test architecture.
Strong experience with industry-standard DFT and implementation tools such as Siemens Tessent, Synopsys Design Compiler and SpyGlass or equivalent tools.
Experience defining and developing scalable DFT flows and methodologies.
Strong knowledge of RTL development and integration using Verilog/SystemVerilog.
Experience integrating multiple IPs and DFT structures into large and complex SoCs.
Good understanding of synthesis, simulation, CDC, lint, RTL quality checks, and design verification methodologies.
Strong understanding of Static Timing Analysis, DFT timing constraints and timing closure.
Experience in Scan/ATPG pattern generation, test-flow development, debug, coverage analysis, and characterization.
Excellent hands-on debugging skills with the ability to drive complex technical issues to closure.
Strong scripting and automation experience using Perl, Python and TCL.
Understanding of low-power design concepts including clock gating and power gating.
Experience with post-silicon bring-up and silicon DFT/debug is highly desirable.
Strong communication, stakeholder-management, and organizational skills with the ability to work effectively across global engineering teams.
Proven ability to balance technical depth, people leadership, program execution, and strategic priorities.
ACADEMIC CREDENTIALS
B.E./B.Tech./M.E./M.Tech. in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
Typically 15+ years of relevant semiconductor/SoC design experience, with significant experience in DFT and technical/team leadership.
#LI-RR1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
