KEY RESPONSIBILITIES
Design and implement RTL for CPU core pipeline components and related logic
Contribute to microarchitecture definition for next-generation processor cores
Collaborate with architecture, verification, and performance teams to deliver optimized designs
Analyze and improve performance, power, and timing characteristics
Support design verification, synthesis, timing closure, and physical design efforts
Debug and resolve pre-silicon and post-silicon issues
Partner with cross-functional teams to align on design trade-offs and execution
Contribute to scalable RTL methodologies, libraries, and best practices
PREFERRED EXPERIENCE
Experience with Verilog/SystemVerilog RTL development in CPU, SoC, or ASIC environments
Strong understanding of modern CPU architecture, especially out-of-order cores
Expertise in logic design and high-speed processor pipeline development
Experience with load / store, cache hierarchy, address translation / TLB, prefetch, branch prediction or similar core subsystems.
Knowledge of power-efficient and low-power design techniques, including timing and power optimization
Familiarity with synthesis, place-and-route, and timing closure
Experience debugging and optimizing designs in collaboration with performance and verification teams
Exposure to the full product lifecycle, from architecture through post-silicon debug
Familiarity with physical design, scripting (e.g., Python, Tcl), and concepts such as DFT, clocking, reset, and power management
ACADEMIC CREDENTIALS
Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field preferred
This role is not eligible for visa sponsorship.
#LI-TB1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
As a CPU Core RTL Design Engineer, you will help design and optimize next-generation high-performance processor cores within AMD’s central core RTL team, which supports a wide range of products across client, server, and AI platforms. Working closely with architecture, performance, verification, and physical design partners, you will contribute to the development of core pipeline logic and microarchitecture features, with flexibility to align to areas such as load/store or decode based on your expertise. This role has direct impact on performance, power efficiency, and scalability of future CPU designs, offering the opportunity to solve complex technical challenges and influence the direction of cutting-edge processor technology.
THE PERSON
You are a strong problem solver with deep curiosity about CPU architecture and a passion for building efficient, high-performance designs. You collaborate effectively across teams, communicate clearly, and can operate independently to drive complex technical challenges to resolution. You bring both critical thinking and creativity, along with the ability to balance performance, power, and timing considerations in modern processor design.
KEY RESPONSIBILITIES
Design and implement RTL for CPU core pipeline components and related logic
Contribute to microarchitecture definition for next-generation processor cores
Collaborate with architecture, verification, and performance teams to deliver optimized designs
Analyze and improve performance, power, and timing characteristics
Support design verification, synthesis, timing closure, and physical design efforts
Debug and resolve pre-silicon and post-silicon issues
Partner with cross-functional teams to align on design trade-offs and execution
Contribute to scalable RTL methodologies, libraries, and best practices
PREFERRED EXPERIENCE
Experience with Verilog/SystemVerilog RTL development in CPU, SoC, or ASIC environments
Strong understanding of modern CPU architecture, especially out-of-order cores
Expertise in logic design and high-speed processor pipeline development
Experience with load / store, cache hierarchy, address translation / TLB, prefetch, branch prediction or similar core subsystems.
Knowledge of power-efficient and low-power design techniques, including timing and power optimization
Familiarity with synthesis, place-and-route, and timing closure
Experience debugging and optimizing designs in collaboration with performance and verification teams
Exposure to the full product lifecycle, from architecture through post-silicon debug
Familiarity with physical design, scripting (e.g., Python, Tcl), and concepts such as DFT, clocking, reset, and power management
ACADEMIC CREDENTIALS
Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field preferred
This role is not eligible for visa sponsorship.
#LI-TB1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
