Develop tools and automation to enhance design verification and engineering efficiency.
Design, verify, and integrate FPGA/ACAP sub-blocks, including RTL and custom design.
Coordinate activities across design teams to enable seamless chip-level integration.
Execute chip-level physical verification.
Execute chip-level electrical verification.
PREFERRED EXPERIENCE
Solid understanding of FPGA architectures.
Hands-on experience with advanced process nodes, including leading-edge 2nm and 3nm technologies.
In-depth knowledge of 2.5D and 3D interposer technologies.
Hands-on experience with physical implementation using one or more industry-standard physical design tools, such as Virtuoso, ICC2, Fusion Compiler (FC), Innovus, or comparable tools.
Strong foundation in circuit design, including hands-on simulation experience with SPICE and Verilog.
Knowledge of or practical experience with Place and Route (P&R) tools and methodologies.
Strong debugging, analytical, and problem-solving skills.
Proficiency in scripting languages such as Perl, Python, TCL, C-shell, Make, or other relevant scripting languages.
Experience working in Unix/Linux environments, including data management and job control.
Excellent written and verbal communication skills, with the ability to collaborate effectively across cross-functional and geographically distributed teams.
ACADEMIC CREDENTIALS
Bachelor’s or Master’s degree in Electrical Engineering or an equivalent field.
LOCATION: San Jose, CA
This role is not eligible for visa sponsorship.
#LI-CJ3
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
AMD’s Adaptive Embedded Computing Group (AECG) develops innovative products that combine high-performance, energy-efficient processors, advanced neural engines, graphics processors, and adaptive computing technologies with programmable logic to enable next-generation edge computing solutions. From autonomous vehicles and industrial robotics to intelligent healthcare devices, AMD AECG is helping redefine the future of intelligent edge computing.
THE PERSON
As a member of the SoC Physical Integration team, you will collaborate closely with cross-functional engineering teams, including Architecture, Design, CAD, Software, and Product Engineering, across multiple geographies. You will contribute to the physical and electrical verification, integration, and tape-out of AMD SoC FPGA/ACAP devices.
KEY RESPONSIBILITIES
Define and develop flows and methodologies for chip-level integration.
Develop tools and automation to enhance design verification and engineering efficiency.
Design, verify, and integrate FPGA/ACAP sub-blocks, including RTL and custom design.
Coordinate activities across design teams to enable seamless chip-level integration.
Execute chip-level physical verification.
Execute chip-level electrical verification.
PREFERRED EXPERIENCE
Solid understanding of FPGA architectures.
Hands-on experience with advanced process nodes, including leading-edge 2nm and 3nm technologies.
In-depth knowledge of 2.5D and 3D interposer technologies.
Hands-on experience with physical implementation using one or more industry-standard physical design tools, such as Virtuoso, ICC2, Fusion Compiler (FC), Innovus, or comparable tools.
Strong foundation in circuit design, including hands-on simulation experience with SPICE and Verilog.
Knowledge of or practical experience with Place and Route (P&R) tools and methodologies.
Strong debugging, analytical, and problem-solving skills.
Proficiency in scripting languages such as Perl, Python, TCL, C-shell, Make, or other relevant scripting languages.
Experience working in Unix/Linux environments, including data management and job control.
Excellent written and verbal communication skills, with the ability to collaborate effectively across cross-functional and geographically distributed teams.
ACADEMIC CREDENTIALS
Bachelor’s or Master’s degree in Electrical Engineering or an equivalent field.
LOCATION: San Jose, CA
This role is not eligible for visa sponsorship.
#LI-CJ3
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
