You bring a thoughtful, analytical approach to problem solving and are comfortable balancing timing, power, area, quality, and schedule considerations. You are also interested in improving design methodologies and identifying opportunities to make engineering flows more efficient and scalable.
KEY RESPONSIBILITIES
Drive physical implementation of high-performance RTL blocks through synthesis, floorplanning, timing-driven place and route, and signoff.
Develop and apply automated design flows for clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and related implementation activities.
Analyze and optimize designs to achieve timing, power, area, physical, and electrical quality targets.
Support floorplanning, design methodology development, and integration of complex IP.
Perform and support logic equivalence, timing, physical, and electrical quality checks.
Troubleshoot implementation and timing challenges and collaboration with design teams to drive issues to closure.
Identify opportunities to improve automation, design methodology, quality, and overall design cycle time.
Support final signoff and delivery of large, high-performance IP blocks.
Build familiarity with the team's design environment and methodologies early in the role, progressing toward independent ownership of physical design blocks and optimization activities.
PREFERRED EXPERIENCE
Experience taking digital designs through the RTL-to-GDS physical design flow.
Experience with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs is preferred.
Experience with automated logic synthesis and timing-driven place and route for high-speed datapath and control logic.
Verilog experience is preferred.
Experience with clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and design optimization.
Knowledge of timing, power, and area optimization techniques.
Understanding of digital circuit techniques, logic optimization, and implementation approaches for high-speed, low-power applications.
Experience with floorplanning, IP integration, logic equivalence checking, physical verification, timing analysis, electrical quality checks, and final signoff.
Experience with industry EDA tools for logic synthesis, place and route, static timing analysis, and physical/electrical design checks.
Familiarity with schematic, layout, circuit simulation, or logic simulation tools is desired.
Experience developing, automating, or improving physical design methodologies and flows is preferred.
ACADEMIC CREDENTIALS
Bachelor's or master’s degree in electrical engineering, Computer Science, or a related technical discipline is preferred.
Relevant technical education or equivalent practical experience in semiconductor or physical design engineering is also valued.
Academic or professional exposure to high-speed SerDes PHY, high-performance digital IP, or related semiconductor design is desired.
LOCATION: Santa Clara
This role is not eligible for visa sponsorship.
#LI-TB2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
Join a team developing high-performance, multi-gigabit SerDes PHY and advanced IP designs. In this Physical Design Engineering role, you will contribute across the full RTL-to-GDS implementation lifecycle, working on challenging designs where timing, power, area, and physical quality are critical.
You will collaborate with geographically distributed engineering teams and gain exposure to synthesis, floorplanning, timing-driven place and route, clock tree synthesis, physical verification, and final sign off. This is an opportunity to influence both individual designs and the methodologies and automated flows used to deliver complex IP efficiently and with high quality.
THE PERSON
The successful candidate is a collaborative and technically curious engineer who enjoys solving complex physical design challenges. You communicate technical concepts clearly, work effectively with colleagues across different disciplines and locations, and can prioritize work across multiple projects.
You bring a thoughtful, analytical approach to problem solving and are comfortable balancing timing, power, area, quality, and schedule considerations. You are also interested in improving design methodologies and identifying opportunities to make engineering flows more efficient and scalable.
KEY RESPONSIBILITIES
Drive physical implementation of high-performance RTL blocks through synthesis, floorplanning, timing-driven place and route, and signoff.
Develop and apply automated design flows for clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and related implementation activities.
Analyze and optimize designs to achieve timing, power, area, physical, and electrical quality targets.
Support floorplanning, design methodology development, and integration of complex IP.
Perform and support logic equivalence, timing, physical, and electrical quality checks.
Troubleshoot implementation and timing challenges and collaboration with design teams to drive issues to closure.
Identify opportunities to improve automation, design methodology, quality, and overall design cycle time.
Support final signoff and delivery of large, high-performance IP blocks.
Build familiarity with the team's design environment and methodologies early in the role, progressing toward independent ownership of physical design blocks and optimization activities.
PREFERRED EXPERIENCE
Experience taking digital designs through the RTL-to-GDS physical design flow.
Experience with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs is preferred.
Experience with automated logic synthesis and timing-driven place and route for high-speed datapath and control logic.
Verilog experience is preferred.
Experience with clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and design optimization.
Knowledge of timing, power, and area optimization techniques.
Understanding of digital circuit techniques, logic optimization, and implementation approaches for high-speed, low-power applications.
Experience with floorplanning, IP integration, logic equivalence checking, physical verification, timing analysis, electrical quality checks, and final signoff.
Experience with industry EDA tools for logic synthesis, place and route, static timing analysis, and physical/electrical design checks.
Familiarity with schematic, layout, circuit simulation, or logic simulation tools is desired.
Experience developing, automating, or improving physical design methodologies and flows is preferred.
ACADEMIC CREDENTIALS
Bachelor's or master’s degree in electrical engineering, Computer Science, or a related technical discipline is preferred.
Relevant technical education or equivalent practical experience in semiconductor or physical design engineering is also valued.
Academic or professional exposure to high-speed SerDes PHY, high-performance digital IP, or related semiconductor design is desired.
LOCATION: Santa Clara
This role is not eligible for visa sponsorship.
#LI-TB2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
