In-depth knowledge on industry leading tools like Primetime and ICC2,
Knowledge of Synthesis and DFT is added advantage.
Knowledge of constraints analysis using GCA or similar tool is added advantage
Prior experience with 3nm or finer geometries is a plus.
Proficient use of tcl/Perl
Must have good communication skills and self-driven individual
ACADEMIC CREDENTIALS
Bachelors or Masters degree in computer engineering/Electrical Engineering with minimum 8-10 years of experience
#LI-PK2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
The focus of this role is to plan and execute full chip timing activities and signoff for advanced chiplets in latest technologies.
THE PERSON
You have a passion for physical design and STA in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES
Experience on Fullchip Timing analysis for multiple modes that includes Functional and DFT and interface special timing checks
To have expertise in understanding and debugging timing issues in Fullchip level and block level.
Experience on Floor-planning, Place & route, power and clock distribution, pin placement.
Role involves interaction with multiple design teams, CAD teams, Tool vendors, (on and cross sites),
In-depth knowledge on industry leading tools like Primetime and ICC2,
Knowledge of Synthesis and DFT is added advantage.
Knowledge of constraints analysis using GCA or similar tool is added advantage
Prior experience with 3nm or finer geometries is a plus.
Proficient use of tcl/Perl
Must have good communication skills and self-driven individual
ACADEMIC CREDENTIALS
Bachelors or Masters degree in computer engineering/Electrical Engineering with minimum 8-10 years of experience
#LI-PK2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
