Block level physical implementation which includes floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layout.
Participate in post-layout circuit performance analysis
Participate in block/IP/chip level integration activities
Estimate realistic schedule, track and report clear progress and status
Strong participation in defining layout methodology and flow
Driving layout productivity improvement initiatives (i.e: pcell development and automation)
Other responsibilities which include supervision of layout resources (onsite and offsite), assessing and correcting layout quality issues, and providing feedback to design teams.
PREFERRED EXPERIENCE
Layout design experience in lower process nodes (7nm or below)
Good understanding of analog and mixed signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heating
Good understanding of high speed critical signal routing and shielding
Strong in physical design verifications (LVS/DRC/ERC/ANT/ESD/etc)
Familiarity with circuit design concepts/flows and IC manufacturing processes
Experience in layout of high-speed SerDes blocks and PLLs in advanced Fin-FET process is a plus
Experience with digital on top integration flow or digital SOC flow is a benefit
Experience with Cadence SKILL and other programming is a benefit (Perl, Python, Tcl, etc ...)
Ability to work closely with the remote & different time zones design teams
Excellent team player and good communication skills
ACADEMIC CREDENTIALS
Bachelor degree in EE/CE or IC layout training Certificate with IC Layout working experience.
LOCATION: San Jose, CA
This role is not eligible for visa sponsorship.
#LI-TB2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
The AMD SerDes Technology Group develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS process. We are currently seeking an experience analog/mixed-signal layout design engineer with supervisory role to join our world-class team in the development of SerDes solutions to facilitate the future connectivity of AMD CPU and GPU products.
THE PERSON
You have a passion for high speed layout design with innovative and creative ideas to solve complex design challenges. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES
Layout design of high speed and high performance SerDes analog mixed signal circuit in accordance to project requirements and specifications.
Block level physical implementation which includes floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layout.
Participate in post-layout circuit performance analysis
Participate in block/IP/chip level integration activities
Estimate realistic schedule, track and report clear progress and status
Strong participation in defining layout methodology and flow
Driving layout productivity improvement initiatives (i.e: pcell development and automation)
Other responsibilities which include supervision of layout resources (onsite and offsite), assessing and correcting layout quality issues, and providing feedback to design teams.
PREFERRED EXPERIENCE
Layout design experience in lower process nodes (7nm or below)
Good understanding of analog and mixed signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heating
Good understanding of high speed critical signal routing and shielding
Strong in physical design verifications (LVS/DRC/ERC/ANT/ESD/etc)
Familiarity with circuit design concepts/flows and IC manufacturing processes
Experience in layout of high-speed SerDes blocks and PLLs in advanced Fin-FET process is a plus
Experience with digital on top integration flow or digital SOC flow is a benefit
Experience with Cadence SKILL and other programming is a benefit (Perl, Python, Tcl, etc ...)
Ability to work closely with the remote & different time zones design teams
Excellent team player and good communication skills
ACADEMIC CREDENTIALS
Bachelor degree in EE/CE or IC layout training Certificate with IC Layout working experience.
LOCATION: San Jose, CA
This role is not eligible for visa sponsorship.
#LI-TB2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
