KEY RESPONSIBILITIES
Develop/Maintain tests for functional verification and performance verification at the core level
Build testbench components to support the next generation IP
Maintain or improve current test libraries to support IP level testing
Develop feature-level verification plans and verify IP across RTL, gate-level simulation, and Analog/Mixed-Signal simulation.
Develop SystemVerilog/UVM-based testbenches, components, sequences, and verification infrastructure.
Execute regressions and drive high-quality verification deliverables.
Develop and close functional coverage, code coverage, and SystemVerilog assertions toward verification completeness.
Review specifications/designs and provide feedback to design and architecture teams.
Provide technical support to other teams
Apply AI tools and agentic workflows to improve verification productivity, including testbench and test development, regression triage, debug, and coverage closure.
PREFERRED EXPERIENCE
Strong SystemVerilog and UVM skills.
Experience with SystemVerilog Assertions (SVA).
Strong understanding of functional and code coverage.
Excellent debugging and problem-solving skills.
Strong digital-design fundamentals and understanding of SoC design flows.
Working knowledge of AI tools and prompt engineering, with hands-on experience applying them to day-to-day verification tasks (e.g., code generation, debug, automation).
Scripting skills (Python, etc.) to build automation and integrate AI-assisted flows into verification environments.
Good communication and cross-functional collaboration skills.
Experience with Memory PHYs DDRPHY, HBMPHY , GDDRPHY and mixed signal verification is a benefit
ACADEMIC CREDENTIALS
Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-PM2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
SENIOR SILICON DESIGN ENGINEER
THE ROLE
We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
The engineer will work on verification of complex Analog/Mixed-Signal IPs with significant digital and analog content, targeted for integration into AMD SoCs.
THE PERSON
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. You are keen about adopting AI to verification and are eager to continuously learn and deploy new AI capabilities in your daily work.
KEY RESPONSIBILITIES
Develop/Maintain tests for functional verification and performance verification at the core level
Build testbench components to support the next generation IP
Maintain or improve current test libraries to support IP level testing
Develop feature-level verification plans and verify IP across RTL, gate-level simulation, and Analog/Mixed-Signal simulation.
Develop SystemVerilog/UVM-based testbenches, components, sequences, and verification infrastructure.
Execute regressions and drive high-quality verification deliverables.
Develop and close functional coverage, code coverage, and SystemVerilog assertions toward verification completeness.
Review specifications/designs and provide feedback to design and architecture teams.
Provide technical support to other teams
Apply AI tools and agentic workflows to improve verification productivity, including testbench and test development, regression triage, debug, and coverage closure.
PREFERRED EXPERIENCE
Strong SystemVerilog and UVM skills.
Experience with SystemVerilog Assertions (SVA).
Strong understanding of functional and code coverage.
Excellent debugging and problem-solving skills.
Strong digital-design fundamentals and understanding of SoC design flows.
Working knowledge of AI tools and prompt engineering, with hands-on experience applying them to day-to-day verification tasks (e.g., code generation, debug, automation).
Scripting skills (Python, etc.) to build automation and integrate AI-assisted flows into verification environments.
Good communication and cross-functional collaboration skills.
Experience with Memory PHYs DDRPHY, HBMPHY , GDDRPHY and mixed signal verification is a benefit
ACADEMIC CREDENTIALS
Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-PM2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
