AMD
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WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices in North America and Asia. Our mandate is to optimize and standardize design methodology, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for complex state-of-the-art APU computing, game console, and GPU graphics products. It is also responsible for DFX design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.
You are a senior leader with extensive knowledge and experience across the areas of DFT and testing. You thrive in an environment that is ‘Lead by influence’ where success is measured by achieving the optimal tradeoff of an often-conflicting set of goals: schedule, Power/Performance/Area, cost and especially quality ( DPPM ). You are looking to nurture deep relationships with Design and Product teams to gather best practices, understand needs, guide the use of tools and flows, and listen to feedback for process improvement. Lastly, you are looking for an opportunity where you can synthesize this input and make a demonstrable impact on a World-Class test strategy; on the innovation of advanced test techniques; on setting industry direction through standards and engagement with the Industry test community; and keeping AMD”s Test Professionals informed and engaged with the creation and execution of a vigorous DFT Roadmap.
Work closely with SOC and PDG teams to drive adoption of and ensure compliance with the company-wide DFT strategy that is continuously aligned with the strategies for the Design, Product Engineering, and Quality functions.
Continually and successfully advocate for maintaining testability features while designs work through various stages, ie floor planning, timing closure, etc.
Follow up with post-silicon experiments to analyze the effectiveness of DFT features to determine their return on investment to justify ongoing usage.
Influence and drive outside partners in the EDA and ATE industries.
Evaluate outside available tools and make decisions on Build vs Buy.
When Build decisions are made, be able to lead and manage a team to architect and implement the internal solution, then see it through to deployment and maintenance.
Extensive and Senior knowledge in DFT and Testing for semiconductor designs.
Proven ability and experience with defining a world-class DFT roadmap strategy.
Proven ability to drive enterprise and cross-department collaboration for DFT across a design organization.
Proven ability and experience partnering with industry leading EDA and ATE companies.
Knowledge with current and industry leading EDA and ATE tools.
Experience developing and deploying internal DFT Tools successfully.
Bachelor’s or Master’s degree in electrical engineering, Computer Engineering, or a related field preferred.
This role is not eligible for visa sponsorship.
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices in North America and Asia. Our mandate is to optimize and standardize design methodology, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for complex state-of-the-art APU computing, game console, and GPU graphics products. It is also responsible for DFX design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.
You are a senior leader with extensive knowledge and experience across the areas of DFT and testing. You thrive in an environment that is ‘Lead by influence’ where success is measured by achieving the optimal tradeoff of an often-conflicting set of goals: schedule, Power/Performance/Area, cost and especially quality ( DPPM ). You are looking to nurture deep relationships with Design and Product teams to gather best practices, understand needs, guide the use of tools and flows, and listen to feedback for process improvement. Lastly, you are looking for an opportunity where you can synthesize this input and make a demonstrable impact on a World-Class test strategy; on the innovation of advanced test techniques; on setting industry direction through standards and engagement with the Industry test community; and keeping AMD”s Test Professionals informed and engaged with the creation and execution of a vigorous DFT Roadmap.
Work closely with SOC and PDG teams to drive adoption of and ensure compliance with the company-wide DFT strategy that is continuously aligned with the strategies for the Design, Product Engineering, and Quality functions.
Continually and successfully advocate for maintaining testability features while designs work through various stages, ie floor planning, timing closure, etc.
Follow up with post-silicon experiments to analyze the effectiveness of DFT features to determine their return on investment to justify ongoing usage.
Influence and drive outside partners in the EDA and ATE industries.
Evaluate outside available tools and make decisions on Build vs Buy.
When Build decisions are made, be able to lead and manage a team to architect and implement the internal solution, then see it through to deployment and maintenance.
Extensive and Senior knowledge in DFT and Testing for semiconductor designs.
Proven ability and experience with defining a world-class DFT roadmap strategy.
Proven ability to drive enterprise and cross-department collaboration for DFT across a design organization.
Proven ability and experience partnering with industry leading EDA and ATE companies.
Knowledge with current and industry leading EDA and ATE tools.
Experience developing and deploying internal DFT Tools successfully.
Bachelor’s or Master’s degree in electrical engineering, Computer Engineering, or a related field preferred.
This role is not eligible for visa sponsorship.
#LI-MR1
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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