2. Key Responsibilities
Hardware, SoC & Platform Architecture
Platform & Systems Architecture: Drive end-to-end dGPU platform definition, evaluating trade-offs across SoC design, power delivery, thermal envelopes, board-level signal/power integrity, and form factors for server, edge, and client systems.
Memory & Interconnect Trade-Offs: Assess memory architecture requirements (GDDR, LPDDR, HBM) alongside memory controller design and compression techniques; optimize high-speed interconnect topologies to maximize bandwidth and system efficiency.
Manageability & Telemetry: Define hardware-level telemetry, power-monitoring, and diagnostics hooks to integrate seamlessly with enterprise manageability platforms (iDRAC, iLO, IPMI) for data center and edge deployments.
Software Architecture & Go-to-Market Readiness
Full-Stack Software Vision: Translate high-level system architectural concepts into concrete software requirements spanning firmware, drivers, runtimes, ROCm libraries, tools, and application layer stacks, across AI, media, visualization, and simulation workloads.
Enterprise & Cloud Enablement: Create long-term software architecture plans of record that ensure seamless integration with Kubernetes orchestration, AI frameworks, and enterprise management tools.
Customer Enablement & Deployment: Author reference architectures, sizing guidance, and tuning guides for customers, ISVs, and systems integrators; support application porting and migration onto the platform; act as the escalation point for failures in a live customer software stack.
Hardware–Software Co-Design & Pre-Silicon Validation
Co-Design Leadership: Lead the hardware/software interface definition, ensuring silicon feature sets directly support software requirements while firmware, driver, and library designs reflect hardware constraints.
Early Silicon & Bring-Up: Serve as a primary technical escalation point during pre-silicon modeling and early post-silicon bring-up; debug complex cross-layer issues spanning physical hardware, firmware, drivers, and application software.
Diagnostics & Workflows: Guide the development of robust diagnostics, pre-silicon emulators, and silicon validation tools to accelerate bring-up schedules across cross-functional engineering teams.
Cross-Functional Leadership & Process Innovation
Cross-Functional Alignment: Collaborate closely across SoC architecture, design verification, hardware engineering, driver development, performance libraries, and product management teams.
AI-Assisted Development: Champion the use of AI-assisted tools to accelerate system modeling, code development, review, and documentation, establishing standards for traceability and validation.
Knowledge Capture: Document reusable architectural patterns, bring-up playbooks, and hardware-software design best practices to scale engineering capability across product generations.
3. Experience & Qualifications
Required Experience & Qualifications
3+/ 7+/ 10+ years of engineering experience in dGPU/SoC platform architecture, hardware engineering, systems software, firmware, or low-level driver development used to bring new silicon to market.
Proven track record in Hardware/Software Co-Design, including defining hardware-software interfaces, analyzing system performance bottlenecks, and debugging complex multi-layer hardware/firmware/software issues.
0 / 0 /2+ years in technical leadership roles with a demonstrated ability to drive technical alignment and resolve ambiguity across multi-disciplinary teams (SoC, platform, drivers, software).
Solid grasp of enterprise manageability standards (IPMI, iDRAC, iLO) and system telemetry frameworks and the software monitoring stacks that operations teams run in production (for example Prometheus, Grafana, OpenTelemetry).
Hands-on experience with containerized GPU deployment and orchestration on Linux and Windows: Docker, Podman, and Kubernetes (including K3s for edge nodes). Experience with Slurm or another cluster scheduler for batch and HPC environments.
Excellent written and verbal communication skills, with the ability to articulate complex architectural trade-offs to both hardware and software audiences.
Willingness to travel domestically and internationally on an occasional basis.
Desired & Optional Qualifications
Machine Learning & AI Frameworks: Knowledge of ML/AI workloads and model architectures (Transformers, Stable Diffusion, CNNs, UNet), including optimization for GPU acceleration libraries (e.g., ROCm, CUDA).
Graphics Architecture: Hands-on experience with DirectX 12, Vulkan, ray tracing pipelines, neural rendering, or game engine performance profiling.
Advanced Systems Engineering: Experience with pre-silicon simulation/emulation environments, server board design, or power integrity analysis.
Production AI Deployment: Experience taking AI workloads from prototype into production: installing and integrating the serving stack (for example vLLM, SGLang, or equivalent), scaling it across nodes, tuning throughput and latency, and handing it over for the customer to operate.
Education: Advanced degree (M.Sc., M.Eng., or Ph.D.) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Job Title: Edge and Enterprise Solution Architect & Systems Engineer
1. General Description of the Role
As an Edge & Enterprise Solution Architect, you will be the core technical authority responsible for defining, architecting, and deploying end-to-end GPU-accelerated computing solutions targeted at enterprise data centers, hybrid cloud environments, and edge platforms. In this role, you will bridge the gap between customer workload requirements and complex system architecture—combining cutting-edge GPU hardware platforms with complete software application stacks to solve real-world enterprise and edge challenges.
You will partner closely with key enterprise customers, ISVs, systems integrators, and internal engineering teams (hardware, firmware, driver, and software stack teams) to translate business needs into robust, scalable, and secure deployment blueprints. Your scope spans the full technology stack: from evaluating underlying GPU compute hardware, thermals, form factors, high-speed interconnects, and enterprise management interfaces (e.g., Redfish, IPMI, iDRAC/iLO) down to configuring AI/ML frameworks, edge orchestration platforms (Kubernetes/K3s), telemetry, security, and domain-specific edge and enterprise application stacks.
2. Key Responsibilities
Hardware, SoC & Platform Architecture
Platform & Systems Architecture: Drive end-to-end dGPU platform definition, evaluating trade-offs across SoC design, power delivery, thermal envelopes, board-level signal/power integrity, and form factors for server, edge, and client systems.
Memory & Interconnect Trade-Offs: Assess memory architecture requirements (GDDR, LPDDR, HBM) alongside memory controller design and compression techniques; optimize high-speed interconnect topologies to maximize bandwidth and system efficiency.
Manageability & Telemetry: Define hardware-level telemetry, power-monitoring, and diagnostics hooks to integrate seamlessly with enterprise manageability platforms (iDRAC, iLO, IPMI) for data center and edge deployments.
Software Architecture & Go-to-Market Readiness
Full-Stack Software Vision: Translate high-level system architectural concepts into concrete software requirements spanning firmware, drivers, runtimes, ROCm libraries, tools, and application layer stacks, across AI, media, visualization, and simulation workloads.
Enterprise & Cloud Enablement: Create long-term software architecture plans of record that ensure seamless integration with Kubernetes orchestration, AI frameworks, and enterprise management tools.
Customer Enablement & Deployment: Author reference architectures, sizing guidance, and tuning guides for customers, ISVs, and systems integrators; support application porting and migration onto the platform; act as the escalation point for failures in a live customer software stack.
Hardware–Software Co-Design & Pre-Silicon Validation
Co-Design Leadership: Lead the hardware/software interface definition, ensuring silicon feature sets directly support software requirements while firmware, driver, and library designs reflect hardware constraints.
Early Silicon & Bring-Up: Serve as a primary technical escalation point during pre-silicon modeling and early post-silicon bring-up; debug complex cross-layer issues spanning physical hardware, firmware, drivers, and application software.
Diagnostics & Workflows: Guide the development of robust diagnostics, pre-silicon emulators, and silicon validation tools to accelerate bring-up schedules across cross-functional engineering teams.
Cross-Functional Leadership & Process Innovation
Cross-Functional Alignment: Collaborate closely across SoC architecture, design verification, hardware engineering, driver development, performance libraries, and product management teams.
AI-Assisted Development: Champion the use of AI-assisted tools to accelerate system modeling, code development, review, and documentation, establishing standards for traceability and validation.
Knowledge Capture: Document reusable architectural patterns, bring-up playbooks, and hardware-software design best practices to scale engineering capability across product generations.
3. Experience & Qualifications
Required Experience & Qualifications
3+/ 7+/ 10+ years of engineering experience in dGPU/SoC platform architecture, hardware engineering, systems software, firmware, or low-level driver development used to bring new silicon to market.
Proven track record in Hardware/Software Co-Design, including defining hardware-software interfaces, analyzing system performance bottlenecks, and debugging complex multi-layer hardware/firmware/software issues.
0 / 0 /2+ years in technical leadership roles with a demonstrated ability to drive technical alignment and resolve ambiguity across multi-disciplinary teams (SoC, platform, drivers, software).
Solid grasp of enterprise manageability standards (IPMI, iDRAC, iLO) and system telemetry frameworks and the software monitoring stacks that operations teams run in production (for example Prometheus, Grafana, OpenTelemetry).
Hands-on experience with containerized GPU deployment and orchestration on Linux and Windows: Docker, Podman, and Kubernetes (including K3s for edge nodes). Experience with Slurm or another cluster scheduler for batch and HPC environments.
Excellent written and verbal communication skills, with the ability to articulate complex architectural trade-offs to both hardware and software audiences.
Willingness to travel domestically and internationally on an occasional basis.
Desired & Optional Qualifications
Machine Learning & AI Frameworks: Knowledge of ML/AI workloads and model architectures (Transformers, Stable Diffusion, CNNs, UNet), including optimization for GPU acceleration libraries (e.g., ROCm, CUDA).
Graphics Architecture: Hands-on experience with DirectX 12, Vulkan, ray tracing pipelines, neural rendering, or game engine performance profiling.
Advanced Systems Engineering: Experience with pre-silicon simulation/emulation environments, server board design, or power integrity analysis.
Production AI Deployment: Experience taking AI workloads from prototype into production: installing and integrating the serving stack (for example vLLM, SGLang, or equivalent), scaling it across nodes, tuning throughput and latency, and handing it over for the customer to operate.
Education: Advanced degree (M.Sc., M.Eng., or Ph.D.) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
