Work with RTL team to debug and sign off power/clock domain crossing violations for project milestones.
PREFERRED EXPERIENCE
Have at least 1 year of experience in feature verification from high level design to tape out verification.
Experience working in simulation, emulation, and formal verification environments.
Power/Clock domain crossing exposure, UPF.
Scripting in Perl or Python.
Leadership skills are a plus!
ACADEMIC CREDENTIALS
Bachelors or Masters degree in Computer Engineering/Electrical Engineering.
This role is not eligible for visa sponsorship.
#LI-LR1329
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
As a Low-Power & CDC Verification Engineer, you will work with formal experts and designers to verify formal properties and drive convergence.
THE PERSON
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES
Review power features for verification scoping and test plan writing.
Coordinate with various teams to develop verification components with various methodologies.
Review and sign off verification deliverables on power features for project milestones.
Work with RTL team to debug and sign off power/clock domain crossing violations for project milestones.
PREFERRED EXPERIENCE
Have at least 1 year of experience in feature verification from high level design to tape out verification.
Experience working in simulation, emulation, and formal verification environments.
Power/Clock domain crossing exposure, UPF.
Scripting in Perl or Python.
Leadership skills are a plus!
ACADEMIC CREDENTIALS
Bachelors or Masters degree in Computer Engineering/Electrical Engineering.
This role is not eligible for visa sponsorship.
#LI-LR1329
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
