KEY RESPONSIBILITIES
Analyze complex digital design problems and propose architecture/micro-architecture solutions
Develop Verilog RTL and Functional Behavioral Models
Drive/develop ASIC design flows and scripts
Create microarchitecture specifications
Work with the Design Verification team to ensure functional correctness
Work with the Physical Design team to ensure proper implementation of the design along with timing closure
Deliver improvements, optimization, and power-saving enhancements
Support silicon bring-up and diagnostics
PREFERRED EXPERIENCE
Proven experience in analog mixed-signal design from specification to successful silicon
Experience in high-speed interfaces such as DDR, GDDR, HBM, and high-speed SERDES.
Experience in designs with multiple power domains
Experience in designs with multiple clock domains
Experience in behavior modeling for Analog Circuits.
Experience in industry-standard ASIC CAD tools for simulation, synthesis, STA, CDC, UPF, power estimation, etc.
ACADEMIC CREDENTIALS
BS/ MS in electrical engineering or equivalent preferred
LOCATION
Santa Clara, CA
#LI-PA1
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
We are looking for an adaptive, self-motivative logic design engineer to join our growing mixed-signal high-speed IO team. As a key contributor, you will be part of a leading team that drives and improves AMD's ability to deliver the highest quality, industry-leading technologies to the market. The Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
THE PERSON
The successful candidate will possess excellent analytical and critical thinking skills with strong attention to detail, demonstrate the initiative and ability to independently drive tasks to successful completion, and communicate effectively across teams and stakeholders. They will bring a collaborative, team-first mindset, contribute positively to a fast-paced environment, and have the ability to mentor and guide junior engineers, fostering both technical growth and team success.
KEY RESPONSIBILITIES
Analyze complex digital design problems and propose architecture/micro-architecture solutions
Develop Verilog RTL and Functional Behavioral Models
Drive/develop ASIC design flows and scripts
Create microarchitecture specifications
Work with the Design Verification team to ensure functional correctness
Work with the Physical Design team to ensure proper implementation of the design along with timing closure
Deliver improvements, optimization, and power-saving enhancements
Support silicon bring-up and diagnostics
PREFERRED EXPERIENCE
Proven experience in analog mixed-signal design from specification to successful silicon
Experience in high-speed interfaces such as DDR, GDDR, HBM, and high-speed SERDES.
Experience in designs with multiple power domains
Experience in designs with multiple clock domains
Experience in behavior modeling for Analog Circuits.
Experience in industry-standard ASIC CAD tools for simulation, synthesis, STA, CDC, UPF, power estimation, etc.
ACADEMIC CREDENTIALS
BS/ MS in electrical engineering or equivalent preferred
LOCATION
Santa Clara, CA
#LI-PA1
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
