KEY RESPONSIBILITIES
Design, implement, and verify FPGA/SoC subsystems for AI edge platforms, including hardware accelerator integration, IP configuration, and design bring-up
Profile and characterize hardware designs — timing closure, resource utilization, power analysis, and thermal behavior — and drive identified issues to resolution
Debug design-specific hardware issues using in-system debug tools (logic analyzers, hardware monitors, JTAG) and correlate findings across RTL, firmware, and software layers
Lead platforms bring-up activities for new AI edge SoC hardware, including boot flow validation, storage subsystem integration, and peripheral initialization
Integrate and validate AI inference runtimes and hardware accelerator stacks on embedded SoC targets, debug performance, correctness, and model deployment issues end-to-end
Support deep learning model compilation, quantization, and optimization workflows targeting embedded AI accelerators (NPU/DPU/spatial compute engines)
Develop and maintain Yocto-based embedded Linux — recipes, layers, rootfs configuration, and kernel/driver integration
Write tooling and automation to support hardware validation, device programming workflows, and CI/CD pipelines
Partner with hardware and silicon teams on system stability, power characterization, and platform validation
Contribute to technical documentation, release notes, and customer-facing enablement content
PREFERRED EXPERIENCE
Hands-on FPGA/SoC design experience: RTL integration, IP configuration
Experience with FPGA design tools (Vivado or equivalent) for implementation, resource analysis, power estimation, and in-system debug
Proficiency with hardware profiling and characterization: performance benchmarking, power/thermal analysis, and design-specific bottleneck identification
Proficiency with low-level hardware debug tools: JTAG, in-system logic analyzers, hardware monitors, signal analyzers
Strong C/C++ development skills with emphasis on embedded and systems-level code quality
Experience with embedded NPU, DPU, or spatial/dataflow AI accelerators — integration, debugging, and performance tuning
Hands-on experience deploying AI inference frameworks on edge or embedded hardware — ONNX Runtime, TensorFlow Lite, TensorRT, or equivalent vendor-specific runtimes
Hands-on Yocto/Open Embedded and embedded Linux experience: BSP bring-up (bootloaders, device trees, kernel drivers), recipe authoring, layer customization, and rootfs configuration
Working knowledge of hardware acceleration concepts: DMA, memory-mapped I/O, PCIe, interrupt handling, shared memory buffers
Experience with GStreamer or comparable multimedia/dataflow pipeline frameworks for hardware-accelerated workloads is a plus
#LI-PK1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Lead System Development Engineer
THE ROLE
AMD is looking for a Lead System Development Engineer to join a team enabling AI inference on AMD's Versal AI Edge SoC platforms. You will work across the full vertical stack — collaborating with embedded Linux, AI runtime, hardware, and platform teams to integrate, validate, and deliver AI solutions on AMD's latest AI Edge hardware. The role spans System design, board bring-up, BSP integration, AI runtime enablement, System characterization, and application pipeline development, with a strong focus on system-level quality and customer readiness
THE PERSON
The ideal candidate operates at the hardware-software boundary — someone who can design and implement FPGA/SoC subsystems, profile and characterize hardware designs, and debug issues that span RTL, firmware, and software layers. You are equally comfortable in a design tool analyzing timing or resource utilization as you are reading a device driver or inference runtime log. You take ownership of complex, cross-layer problems and drive them to resolution independently.
KEY RESPONSIBILITIES
Design, implement, and verify FPGA/SoC subsystems for AI edge platforms, including hardware accelerator integration, IP configuration, and design bring-up
Profile and characterize hardware designs — timing closure, resource utilization, power analysis, and thermal behavior — and drive identified issues to resolution
Debug design-specific hardware issues using in-system debug tools (logic analyzers, hardware monitors, JTAG) and correlate findings across RTL, firmware, and software layers
Lead platforms bring-up activities for new AI edge SoC hardware, including boot flow validation, storage subsystem integration, and peripheral initialization
Integrate and validate AI inference runtimes and hardware accelerator stacks on embedded SoC targets, debug performance, correctness, and model deployment issues end-to-end
Support deep learning model compilation, quantization, and optimization workflows targeting embedded AI accelerators (NPU/DPU/spatial compute engines)
Develop and maintain Yocto-based embedded Linux — recipes, layers, rootfs configuration, and kernel/driver integration
Write tooling and automation to support hardware validation, device programming workflows, and CI/CD pipelines
Partner with hardware and silicon teams on system stability, power characterization, and platform validation
Contribute to technical documentation, release notes, and customer-facing enablement content
PREFERRED EXPERIENCE
Hands-on FPGA/SoC design experience: RTL integration, IP configuration
Experience with FPGA design tools (Vivado or equivalent) for implementation, resource analysis, power estimation, and in-system debug
Proficiency with hardware profiling and characterization: performance benchmarking, power/thermal analysis, and design-specific bottleneck identification
Proficiency with low-level hardware debug tools: JTAG, in-system logic analyzers, hardware monitors, signal analyzers
Strong C/C++ development skills with emphasis on embedded and systems-level code quality
Experience with embedded NPU, DPU, or spatial/dataflow AI accelerators — integration, debugging, and performance tuning
Hands-on experience deploying AI inference frameworks on edge or embedded hardware — ONNX Runtime, TensorFlow Lite, TensorRT, or equivalent vendor-specific runtimes
Hands-on Yocto/Open Embedded and embedded Linux experience: BSP bring-up (bootloaders, device trees, kernel drivers), recipe authoring, layer customization, and rootfs configuration
Working knowledge of hardware acceleration concepts: DMA, memory-mapped I/O, PCIe, interrupt handling, shared memory buffers
Experience with GStreamer or comparable multimedia/dataflow pipeline frameworks for hardware-accelerated workloads is a plus
#LI-PK1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
