KEY RESPONSIBILITIES
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Drive Emulation Methodologies, SOC Design Model and Test Architecture for full chip SOC and hybrid models
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed Pre-Silicon Emulation tests
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test or infra issues
Responsible for writing directed tests to verify features in a co-simulated and emulated/FPGA hardware environment
Responsible for writing monitors and checkers to support end-to-end firmware/hardware validation
Responsible for running emulator workloads to test new features and debug technical issues using logs, waveform dumps and RTL debug
Use AI for hardware debug, improve execution and emulation capacity efficiency and automation
PREFERRED EXPERIENCE
Must have exposure to SOC architecture (preferred X86)
Experience with BIOS/OS bring up on full X86 SOC emulation platform
Proficient in IP level ASIC verification, experience working with CPU, GPU, and Memory subsystem
Proficient in debugging firmware and RTL code using simulation tools
Good understanding of PCIe/USB/Ethernet standards; safety concepts/IPs
Must have hands-on experience on Zebu/Palladium/Veloce platform to bring-up SOC
SOC design model build experience
Experienced with Verilog, System Verilog, C, and C++
Experience in writing and debugging testbenches
Scripting language experience: Perl, Ruby, Makefile, shell preferred
Experience on debugging SOC IO interfaces with Transactor solutions in Emulation platform
Think differently and out of the box to stress the DUT in Emulation platform and verify it in efficient way
Should be open to learning verification methodologies and working closely with design, verification, validation, architecture and firmware teams
Excellent communication, management, and presentation skills
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
ACADEMIC CREDENTIALS
Bachelor’s or Master’s degree in Computer/Electronics/Electrical Engineering with 18+ years of experience
#L1-RG2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
LEAD PLATFORM EMULATION ENGINEER
THE ROLE
The focus of this role is to plan, build, execute the verification, validation/emulation and debug of new and existing features for AMD’s SOCs, resulting in no bugs in the final SOC design and the firmware/BIOS. This senior role will stretch you as you lead emulation team in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives.
THE PERSON
You have a passion for modern, complex processor architecture, digital design, and verification/debugging in general. You are a team player who has experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems
You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.
KEY RESPONSIBILITIES
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Drive Emulation Methodologies, SOC Design Model and Test Architecture for full chip SOC and hybrid models
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed Pre-Silicon Emulation tests
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test or infra issues
Responsible for writing directed tests to verify features in a co-simulated and emulated/FPGA hardware environment
Responsible for writing monitors and checkers to support end-to-end firmware/hardware validation
Responsible for running emulator workloads to test new features and debug technical issues using logs, waveform dumps and RTL debug
Use AI for hardware debug, improve execution and emulation capacity efficiency and automation
PREFERRED EXPERIENCE
Must have exposure to SOC architecture (preferred X86)
Experience with BIOS/OS bring up on full X86 SOC emulation platform
Proficient in IP level ASIC verification, experience working with CPU, GPU, and Memory subsystem
Proficient in debugging firmware and RTL code using simulation tools
Good understanding of PCIe/USB/Ethernet standards; safety concepts/IPs
Must have hands-on experience on Zebu/Palladium/Veloce platform to bring-up SOC
SOC design model build experience
Experienced with Verilog, System Verilog, C, and C++
Experience in writing and debugging testbenches
Scripting language experience: Perl, Ruby, Makefile, shell preferred
Experience on debugging SOC IO interfaces with Transactor solutions in Emulation platform
Think differently and out of the box to stress the DUT in Emulation platform and verify it in efficient way
Should be open to learning verification methodologies and working closely with design, verification, validation, architecture and firmware teams
Excellent communication, management, and presentation skills
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
ACADEMIC CREDENTIALS
Bachelor’s or Master’s degree in Computer/Electronics/Electrical Engineering with 18+ years of experience
#L1-RG2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
