THE PERSON
The ideal candidate has worked on FPGA devices, programmable logic architecture, digital circuit design, timing characterization, or device modeling. We are particularly interested in candidates who understand the internal circuitry and architecture of programmable devices, rather than only using commercial FPGAs to implement end applications.
KEY RESPONSIBLITIES
Generate simulation based delays using existing hardware designs to match FPGA timing arcs as per the device model
Develop automation flows to improve FPGA timing quality.
Drive silicon based characterization of FPGA resources and root cause any mis-correlation with the expected timing model.
Performance analysis on complex designs using Vivado tool
Coordinate release readiness reviews and manage risk mitigation plans.
Train junior team members and deliver on time results with quality
PREFERRED EXPERIENCE
Digital circuit design and FPGA device architecture
FPGA design implementation and performance analysis
Static Timing Analysis and timing-model fundamentals
Simulation and silicon characterization
PrimeTime, SPICE, and Vivado
CAD or engineering flow development
Python, Tcl, Perl, databases, and software algorithms
FPGA device modeling, timing characterization, or speed-file experience
ACADEMIC CREDENTIALS
Bachelors or Masters degree in Computer Science/Electrical Engineering
LOCATION: San Jose, CA
This role is not eligible for visa sponsorship.
#LI-DR2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
As a Senior FPGA Design & Timing Modeling Engineer, you will work at the intersection of FPGA circuit design, silicon characterization, and software device modeling. You will help translate the behavior and performance of AMD FPGA hardware into accurate timing models used by Vivado to compile, analyze, and optimize customer designs.
This role requires a strong understanding of digital circuits and FPGA device architecture, combined with experience in timing analysis, simulation, silicon characterization, and engineering automation. You will investigate differences between simulated, modeled, and measured silicon performance and develop new methodologies to improve timing accuracy and reduce unnecessary design margins.
As a leading AI company, we will be leveraging all the available AI capabilities in the market today along with the many internal solutions available at AMD. You will need to work with cross functional teams like front-end design, circuit design, custom layout design, place and route, device modeling and device capture. You will be expected to innovate and deliver results, prioritizing critical tasks, and enable successful production release of Vivado’s timing for every programmable device.
THE PERSON
The ideal candidate has worked on FPGA devices, programmable logic architecture, digital circuit design, timing characterization, or device modeling. We are particularly interested in candidates who understand the internal circuitry and architecture of programmable devices, rather than only using commercial FPGAs to implement end applications.
KEY RESPONSIBLITIES
Generate simulation based delays using existing hardware designs to match FPGA timing arcs as per the device model
Develop automation flows to improve FPGA timing quality.
Drive silicon based characterization of FPGA resources and root cause any mis-correlation with the expected timing model.
Performance analysis on complex designs using Vivado tool
Coordinate release readiness reviews and manage risk mitigation plans.
Train junior team members and deliver on time results with quality
PREFERRED EXPERIENCE
Digital circuit design and FPGA device architecture
FPGA design implementation and performance analysis
Static Timing Analysis and timing-model fundamentals
Simulation and silicon characterization
PrimeTime, SPICE, and Vivado
CAD or engineering flow development
Python, Tcl, Perl, databases, and software algorithms
FPGA device modeling, timing characterization, or speed-file experience
ACADEMIC CREDENTIALS
Bachelors or Masters degree in Computer Science/Electrical Engineering
LOCATION: San Jose, CA
This role is not eligible for visa sponsorship.
#LI-DR2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
