The right candidate brings deep hands-on expertise in GFX pipeline and SOC architecture and debug, combined with the management maturity to coach engineers, drive cross-functional alignment, and deliver predictably on complex multi-quarter programs.
THE PERSON
We are looking for a mature engineering leader who leads by example: someone who can roll up their sleeves on a hard debug problem one moment and run a productive one-on-one the next. The ideal candidate has a proven track record of building new teams, developing engineers' technical and professional skills, and fostering a culture of ownership, rigor, and continuous improvement. Critical thinking, clear communication, and the ability to translate complex architectural tradeoffs into actionable engineering priorities are essential.
KEY RESPONSIBILITIES
Team Building & People Development
Recruit, hire, and onboard firmware engineers across all experience levels to build a world-class Data Center GFX FW team from the ground up.
Develop and execute structured onboarding and ramp-up plans that accelerate new engineer productivity, including mentorship programs, technical deep-dives, and hands-on coding expectations.
Conduct regular one-on-ones, performance reviews, and career development planning; identify high-potential engineers and create growth paths for advancement.
Foster a collaborative, inclusive team culture grounded in technical excellence, psychological safety, and accountability.
Establish team norms, coding standards, firmware review processes, and documentation practices.
Technical Leadership & Architecture
Own the firmware architecture for GFX compute and data center workloads, including RLC (Run List Controller) microcode design, scheduling, power gating sequences, and SOC-level initialization flows.
Drive SOC debug strategies across the ASIC lifecycle — from emulation and pre-silicon simulation through first silicon and production; serve as the escalation point for complex, cross-team debug campaigns.
Collaborate closely with GFX hardware architects, RTL designers, driver teams, and platform software engineers to co-define firmware/hardware interfaces and feature specifications.
Provide technical direction on power and performance management features, memory controller interactions, interrupt handling, and firmware security primitives.
Review and approve firmware architecture documents, micro-architecture specs, and critical firmware changes.
Program Execution & Delivery
Define, track, and communicate team goals, milestone plans, and risk areas to senior leadership and partner teams.
Own the firmware feature roadmap for Data Center GFX; balance short-term silicon commitments with long-term architectural investment.
Drive continuous improvement in firmware quality, test coverage, bring-up velocity, and release reliability.
Manage cross-functional dependencies with hardware, software, platform, and validation teams to ensure smooth program execution.
PREFERRED EXPERIENCE
Experienced in semiconductor firmware, embedded systems, or SOC software engineering, with a focus in an engineering management or tech lead-manager role.
Proven record of building new engineering teams: hiring, onboarding, and growing engineers from junior to senior level in a fast-paced semiconductor environment.
Deep expertise in GFX or SOC architecture, design, and debug — including microcode authoring, scheduling algorithms, and bring-up.
Strong SOC-level debug skills: proficiency with hardware trace tools, logic analyzers, oscilloscopes, JTAG, and post-silicon debug methodologies across complex multi-IP SOCs.
Hands-on firmware development experience in C and assembly for embedded microcontrollers (e.g., MEC, PSP, RLC, PMFW cores, or similar GPU/SOC control processors).
Solid understanding of GFX/GPU architecture: command processors, shader engines, memory subsystems, power domains, and clock gating.
Experience with FPGA-based emulation (e.g., Palladium, Veloce) and pre-silicon firmware validation.
Track record of mentoring and developing engineers; experience implementing structured onboarding programs, technical training curricula, or engineering ladders.
Excellent cross-functional collaboration and communication skills; ability to represent firmware perspective in architecture reviews and executive program updates.
Familiarity with Python, scripting-based test automation, and firmware CI/CD pipelines is a plus.
Security/cryptography firmware experience is an asset.
ACADEMIC CREDENTIALS
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science; PhD is a plus.
LOCATION
Markham, ON, Canada
This role is not eligible for Visa Sponsorship.
#LI-CB1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
We are a high-impact, forward-thinking firmware team dedicated to advancing Data Center Graphics Processing Units (GPUs) and Machine Intelligence Processing Units. Our mission spans the full ASIC lifecycle — from architecture and RTL collaboration through emulation, silicon bring-up, production enablement, and customer escalation support. We are passionate about GFX FW (Run List Controller) architecture, SOC-level debug, power and performance management, and building the firmware foundation that unlocks the potential of AMD's next-generation data center platforms.
We are seeking a seasoned firmware engineering manager to lead and grow the Data Center GFX FW team. This is a greenfield leadership opportunity: you will be responsible for building the team from the ground up, recruiting top firmware talent, establishing engineering culture and processes, and accelerating the ramp-up of engineers at all levels. You will set the technical direction for GFX firmware features and own execution from concept through production.
The right candidate brings deep hands-on expertise in GFX pipeline and SOC architecture and debug, combined with the management maturity to coach engineers, drive cross-functional alignment, and deliver predictably on complex multi-quarter programs.
THE PERSON
We are looking for a mature engineering leader who leads by example: someone who can roll up their sleeves on a hard debug problem one moment and run a productive one-on-one the next. The ideal candidate has a proven track record of building new teams, developing engineers' technical and professional skills, and fostering a culture of ownership, rigor, and continuous improvement. Critical thinking, clear communication, and the ability to translate complex architectural tradeoffs into actionable engineering priorities are essential.
KEY RESPONSIBILITIES
Team Building & People Development
Recruit, hire, and onboard firmware engineers across all experience levels to build a world-class Data Center GFX FW team from the ground up.
Develop and execute structured onboarding and ramp-up plans that accelerate new engineer productivity, including mentorship programs, technical deep-dives, and hands-on coding expectations.
Conduct regular one-on-ones, performance reviews, and career development planning; identify high-potential engineers and create growth paths for advancement.
Foster a collaborative, inclusive team culture grounded in technical excellence, psychological safety, and accountability.
Establish team norms, coding standards, firmware review processes, and documentation practices.
Technical Leadership & Architecture
Own the firmware architecture for GFX compute and data center workloads, including RLC (Run List Controller) microcode design, scheduling, power gating sequences, and SOC-level initialization flows.
Drive SOC debug strategies across the ASIC lifecycle — from emulation and pre-silicon simulation through first silicon and production; serve as the escalation point for complex, cross-team debug campaigns.
Collaborate closely with GFX hardware architects, RTL designers, driver teams, and platform software engineers to co-define firmware/hardware interfaces and feature specifications.
Provide technical direction on power and performance management features, memory controller interactions, interrupt handling, and firmware security primitives.
Review and approve firmware architecture documents, micro-architecture specs, and critical firmware changes.
Program Execution & Delivery
Define, track, and communicate team goals, milestone plans, and risk areas to senior leadership and partner teams.
Own the firmware feature roadmap for Data Center GFX; balance short-term silicon commitments with long-term architectural investment.
Drive continuous improvement in firmware quality, test coverage, bring-up velocity, and release reliability.
Manage cross-functional dependencies with hardware, software, platform, and validation teams to ensure smooth program execution.
PREFERRED EXPERIENCE
Experienced in semiconductor firmware, embedded systems, or SOC software engineering, with a focus in an engineering management or tech lead-manager role.
Proven record of building new engineering teams: hiring, onboarding, and growing engineers from junior to senior level in a fast-paced semiconductor environment.
Deep expertise in GFX or SOC architecture, design, and debug — including microcode authoring, scheduling algorithms, and bring-up.
Strong SOC-level debug skills: proficiency with hardware trace tools, logic analyzers, oscilloscopes, JTAG, and post-silicon debug methodologies across complex multi-IP SOCs.
Hands-on firmware development experience in C and assembly for embedded microcontrollers (e.g., MEC, PSP, RLC, PMFW cores, or similar GPU/SOC control processors).
Solid understanding of GFX/GPU architecture: command processors, shader engines, memory subsystems, power domains, and clock gating.
Experience with FPGA-based emulation (e.g., Palladium, Veloce) and pre-silicon firmware validation.
Track record of mentoring and developing engineers; experience implementing structured onboarding programs, technical training curricula, or engineering ladders.
Excellent cross-functional collaboration and communication skills; ability to represent firmware perspective in architecture reviews and executive program updates.
Familiarity with Python, scripting-based test automation, and firmware CI/CD pipelines is a plus.
Security/cryptography firmware experience is an asset.
ACADEMIC CREDENTIALS
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science; PhD is a plus.
LOCATION
Markham, ON, Canada
This role is not eligible for Visa Sponsorship.
#LI-CB1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
