AMD
From AMD's careers page
Status: listed on the employer's own careers page when we last checked (daily). Confirm on their site before applying.
LOCATION: Boxborough, MA #LI-SL3 This role is not eligible for visa sponsorship.
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Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
We are searching for a senior technical leader to join CT DDR PHY development team, responsible for driving system architecture and circuit specifications for leading edge memory interface and die-to-die interconnects. The successful candidate will be expected to build end-to-end link model and define circuit specifications, adaptation and training algorithms for circuit and firmware engineers.
THE PERSON
A proven successful track record and deep technical knowledge in system architecture for high-speed interconnects
Strong and effective communication skills
Proven technical leadership and partner well with circuit, firmware, verification and post-silicon validation teams
Mentor junior engineers
Bachelor’s degree with at least 15 years of relevant experience; MS/PhD preferred
Lead system architecture development, build end-to-end link model and define circuit specifications
Define adaptation and training algorithms for next generation PHYs
Hands-on leadership in all phases of the project from conception through execution and production
Partner with other teams including domain and technical leads, architects, SI/PI, AMS, RTL, SOC, DV and post-silicon validation engineers to ensure interlocked execution
Provide over-all technical leadership and contribute to shared methodologies across pre-silicon and post-silicon teams
deep technical knowledge in system architecture for high-speed interconnects
system architecture development, build end-to-end link model and define circuit specifications
technical leadership and partner well with circuit, firmware, verification and post-silicon validation teams
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
Master's degree preferred.
#LI-SL3
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
We are searching for a senior technical leader to join CT DDR PHY development team, responsible for driving system architecture and circuit specifications for leading edge memory interface and die-to-die interconnects. The successful candidate will be expected to build end-to-end link model and define circuit specifications, adaptation and training algorithms for circuit and firmware engineers.
THE PERSON
A proven successful track record and deep technical knowledge in system architecture for high-speed interconnects
Strong and effective communication skills
Proven technical leadership and partner well with circuit, firmware, verification and post-silicon validation teams
Mentor junior engineers
Bachelor’s degree with at least 15 years of relevant experience; MS/PhD preferred
Lead system architecture development, build end-to-end link model and define circuit specifications
Define adaptation and training algorithms for next generation PHYs
Hands-on leadership in all phases of the project from conception through execution and production
Partner with other teams including domain and technical leads, architects, SI/PI, AMS, RTL, SOC, DV and post-silicon validation engineers to ensure interlocked execution
Provide over-all technical leadership and contribute to shared methodologies across pre-silicon and post-silicon teams
deep technical knowledge in system architecture for high-speed interconnects
system architecture development, build end-to-end link model and define circuit specifications
technical leadership and partner well with circuit, firmware, verification and post-silicon validation teams
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
Master's degree preferred.
#LI-SL3
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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