- Partner with Architecture and STA teams to establish timing budgets, statistical timing targets and signoff criteria.
- Analyze and manage advanced-node timing margins including LVF, SSTA, OCV/AOCV/POCV and variation-aware signoff methodologies.
Lead timing ECO planning and execution to ensure on-time tapeout.
Collaborate with CAD and EDA vendors to improve timing closure flows, automation and methodologies.
Mentor engineers and provide technical leadership for timing closure activities across multiple projects.
PREFERRED EXPERIENCE
- 14+ years of experience in Physical Design, Static Timing Analysis, Constraints Development and Timing Signoff.
- Strong expertise in:
- Full Chip Timing Closure
- STA Signoff
- Timing Constraints (SDC)
- Timing ECO Methodologies
- Advanced Node Timing Signoff
- Clock Architecture and Clock Implementation
- MCMM Timing Analysis
- DFT Timing and MBIST Timing Verification
- Hands-on experience with Synopsys PrimeTime (PT) and GCA.
- Experience with Fusion Compiler and/or ICC2 is highly desirable.
- Strong understanding of floorplanning, placement, CTS and routing interactions with timing.
- Proficiency in Tcl, Perl, Shell and Python scripting
Leadership Expectations
Provide technical leadership for Full Chip Timing execution across multiple programs.
Drive cross-functional alignment among Architecture, Design, PD, DFT and CAD teams.
Mentor MTS/SDE engineers and develop future FCT leads.
Influence timing methodologies and signoff strategies for upcoming technology nodes.
ACADEMIC CREDENTIALS
Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-BM2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
FCT LEAD
THE ROLE
As an FCT Lead within the Physical Design organisation, you will lead Full Chip Timing (FCT) execution and timing signoff activities for complex SoC and subsystem designs. You will work closely with Architecture, Design, PD, STA, DFT, CAD and Methodology teams to achieve first-pass silicon success and deliver timing closure for industry-leading products
THE PERSON
A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
KEY RESPONSIBLITIES
Lead the Full Chip Timing team responsible for timing constraints development and timing signoff.
Own end-to-end timing closure and signoff for SoC and subsystem integration projects.
Define, develop and validate SDC constraints, clocks and timing methodologies.
Drive timing convergence across synthesis, P&R, CTS, route and post-route ECO stages.
- Partner with Architecture and STA teams to establish timing budgets, statistical timing targets and signoff criteria.
- Analyze and manage advanced-node timing margins including LVF, SSTA, OCV/AOCV/POCV and variation-aware signoff methodologies.
Lead timing ECO planning and execution to ensure on-time tapeout.
Collaborate with CAD and EDA vendors to improve timing closure flows, automation and methodologies.
Mentor engineers and provide technical leadership for timing closure activities across multiple projects.
PREFERRED EXPERIENCE
- 14+ years of experience in Physical Design, Static Timing Analysis, Constraints Development and Timing Signoff.
- Strong expertise in:
- Full Chip Timing Closure
- STA Signoff
- Timing Constraints (SDC)
- Timing ECO Methodologies
- Advanced Node Timing Signoff
- Clock Architecture and Clock Implementation
- MCMM Timing Analysis
- DFT Timing and MBIST Timing Verification
- Hands-on experience with Synopsys PrimeTime (PT) and GCA.
- Experience with Fusion Compiler and/or ICC2 is highly desirable.
- Strong understanding of floorplanning, placement, CTS and routing interactions with timing.
- Proficiency in Tcl, Perl, Shell and Python scripting
Leadership Expectations
Provide technical leadership for Full Chip Timing execution across multiple programs.
Drive cross-functional alignment among Architecture, Design, PD, DFT and CAD teams.
Mentor MTS/SDE engineers and develop future FCT leads.
Influence timing methodologies and signoff strategies for upcoming technology nodes.
ACADEMIC CREDENTIALS
Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-BM2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
