Interact with multiple stakeholders (firmware/BIOS, RTL designers, DV, system architects) to plan, create, execute, and debug core on emulators
Defining and implementing test plans including stimulus, checking and functional coverage plans
Developing test benches and test bench components in C++
Responsible for writing monitors and checkers to support end-to-end core emulation infrastructure
Debugging regression fails and fixing verification issues or working with designers to fix design bugs
Assist with silicon observations often requiring replication of behaviors in simulation to root cause
Responsible for running emulator workloads to test all new features
Create hardware emulation build to verify the IP functional performance
Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
Provide technical support to other teams
PREFERRED EXPERIENCE
Experienced with FPGA and/or emulation platforms (ZeBu, HAPs, Veloce)
Experienced with Verilog, System Verilog, C, and C++
Experienced debugging failures using waveform viewers, log files, and microcode trace dumps
Strong background in the C++ language, preferably on Linux with exposure to Windows platform
Automating workflows in a distributed compute environment
Knowledge of UEFI, core-boot, Linux, Windows Operating Systems
Knowledge of x86 and/or ARM SoC Architecture
Coding in x86 Assembly language
Proficient in debugging firmware and RTL code using simulation tools
Proficient in using UVM testbenches and working in Linux and Windows environments
Scripting language experience: Perl, Python, Makefile, shell preferred
Exposure to leadership or mentorship is an asset
ACADEMIC CREDENTIALS
Bachelors or Masters degree in computer engineering/Electrical Engineering
This role is not eligible for visa sponsorship.
#LI-MR1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification/Emulation Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
THE PERSON
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES
Come join the team responsible for driving AMD Core’s Shift-Left strategies
Interact with multiple stakeholders (firmware/BIOS, RTL designers, DV, system architects) to plan, create, execute, and debug core on emulators
Defining and implementing test plans including stimulus, checking and functional coverage plans
Developing test benches and test bench components in C++
Responsible for writing monitors and checkers to support end-to-end core emulation infrastructure
Debugging regression fails and fixing verification issues or working with designers to fix design bugs
Assist with silicon observations often requiring replication of behaviors in simulation to root cause
Responsible for running emulator workloads to test all new features
Create hardware emulation build to verify the IP functional performance
Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
Provide technical support to other teams
PREFERRED EXPERIENCE
Experienced with FPGA and/or emulation platforms (ZeBu, HAPs, Veloce)
Experienced with Verilog, System Verilog, C, and C++
Experienced debugging failures using waveform viewers, log files, and microcode trace dumps
Strong background in the C++ language, preferably on Linux with exposure to Windows platform
Automating workflows in a distributed compute environment
Knowledge of UEFI, core-boot, Linux, Windows Operating Systems
Knowledge of x86 and/or ARM SoC Architecture
Coding in x86 Assembly language
Proficient in debugging firmware and RTL code using simulation tools
Proficient in using UVM testbenches and working in Linux and Windows environments
Scripting language experience: Perl, Python, Makefile, shell preferred
Exposure to leadership or mentorship is an asset
ACADEMIC CREDENTIALS
Bachelors or Masters degree in computer engineering/Electrical Engineering
This role is not eligible for visa sponsorship.
#LI-MR1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
