KEY RESPONSIBILITIES
Use Cadence tools for design, modeling and simulations. Enable timely closure of designs by getting involved with pre-design negotiations with chip/system teams and take it to design sign off.
Use analytical and simulation tools to define package/module design requirements (technology, stack-up, etc.) in the project conception stages and negotiate with chip/system teams on product specification.
Conduct routing, stack-up & component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stack-up, manufacturing time etc) for various device packaging.
Collaborate with PCB Layout Engineers to optimize the package ballmap and chip team to optimize the die size.
Develop multi-signal package/module models over 50 GHz bandwidth and suitable test structures for model to measurement correlation.
Come up with performance metrics for organic package technologies in order to design high speed chips and systems.
Performing Power Integrity analysis for core as well as IO and generate power delivery network requirements with emphasis on model to measurement correlation.
Develop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations.
PREFERRED EXPERIENCE
Have a good understanding of various Organic/PCB technologies in order to interpret/negotiate layout guidelines.
Package/PCB layout experience. Experience in high power, Gbs IO products is a plus.
Current working Knowledge of Cadence package design tool is a must. knowledge of SKILL is a plus.
Working knowledge of 2D/3D package design and modeling tools, such as Cadence, Ansys, AutoCAD etc.
Knowledge on DoE, DFM/DFR is a plus.
Good knowledge of SerDes design and package/PCB layout constraints.
Mentor junior package designers in the group.
ACADEMIC CREDENTIALS
Bachelor’s or Master's degree in Engineering
LOCATION: San Jose, CA ; San Diego, CA
#LI-RW1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE TEAM
The AECG - Embedded Team builds and optimizes platforms for embedded and commercial applications, working across silicon, firmware, and software to deliver reliable, high‑performance solutions at scale.
THE ROLE
The AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated electrical package design engineer. As a key member of the Package group, you will work across chip, technology and systems teams to define cost effective and high performance solutions.
THE PERSON
This is a high visibility position working on multiple package families for the FPGA devices. The ideal candidate should have the ability to understand electrical requirements and translate to the proper package technology requirements that is cost effective and manufacturable. This role requires good communication skills to work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages.
KEY RESPONSIBILITIES
Use Cadence tools for design, modeling and simulations. Enable timely closure of designs by getting involved with pre-design negotiations with chip/system teams and take it to design sign off.
Use analytical and simulation tools to define package/module design requirements (technology, stack-up, etc.) in the project conception stages and negotiate with chip/system teams on product specification.
Conduct routing, stack-up & component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stack-up, manufacturing time etc) for various device packaging.
Collaborate with PCB Layout Engineers to optimize the package ballmap and chip team to optimize the die size.
Develop multi-signal package/module models over 50 GHz bandwidth and suitable test structures for model to measurement correlation.
Come up with performance metrics for organic package technologies in order to design high speed chips and systems.
Performing Power Integrity analysis for core as well as IO and generate power delivery network requirements with emphasis on model to measurement correlation.
Develop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations.
PREFERRED EXPERIENCE
Have a good understanding of various Organic/PCB technologies in order to interpret/negotiate layout guidelines.
Package/PCB layout experience. Experience in high power, Gbs IO products is a plus.
Current working Knowledge of Cadence package design tool is a must. knowledge of SKILL is a plus.
Working knowledge of 2D/3D package design and modeling tools, such as Cadence, Ansys, AutoCAD etc.
Knowledge on DoE, DFM/DFR is a plus.
Good knowledge of SerDes design and package/PCB layout constraints.
Mentor junior package designers in the group.
ACADEMIC CREDENTIALS
Bachelor’s or Master's degree in Engineering
LOCATION: San Jose, CA ; San Diego, CA
#LI-RW1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
