KEY RESPONSIBILTIIES
Strategic Technical Leadership: Define the technical roadmap, architecture, and deployment strategy for migrating post-silicon SLT and functional GFX IP feature diagnostics onto various testing and validation platforms
Pattern Generation & Conversion: Architect and develop software utilities/pipelines to convert functional diagnostic sequences, register configurations, and compute workloads into cycle-accurate vector formats (e.g., STIL, WGL, or proprietary tester formats) compatible with modern testers.
Cross-Domain Collaboration: Serve as the primary technical liaison between the GFX/Compute Diagnostics team, Product/Test Engineering, and Design-for-Test (DFT) teams, analyzing and root causing RTL bugs and improving pre-silicon coverage
Platform Integration & Emulation: Analyze existing platform-level hardware/software dependencies (such as sideband management interfaces, firmware, and power management behaviors) to build deterministic, tester-friendly models that emulate host behaviors on multiple hardware platforms
Test Coverage & Cost Optimization: Optimize tester execution times (test cost reduction) while maximizing structural and functional test coverage for data center GPU IPs, focusing on massively parallel compute pipelines, high-bandwidth memory (HBM) controllers, and matrix math engines.
PREFERRED EXPERIENCE
Experience: Proven industry experience in silicon engineering spanning post-silicon validation, product engineering, diagnostics development, or structural/functional test generation.
Platform HW/SW Proficiency: Strong programming background in C/C++ and Python, with a concrete understanding of bare-metal or driver-level programming, registers, firmware interactions, and system memory maps
Pattern Flow Knowledge: Expert understanding of structural pattern generation, vector timing, clock domains, and diagnostic patterns (such as functional vectors, BIST/MBIST, or scan compression output).
Familiarity with high-volume manufacturing challenges unique to data center architectures, including high-power profiles, HBM integration, and multi-die chiplet interconnect protocols (e.g., UCIe, proprietary fabrics).
Deep understanding of GFX and compute architectures, with proven ability to design and implement diagnostic and test cases that maximize coverage and proactively identify silicon issues early
Understanding of AI/ML principles and some experience in applying LLM & ML models in applications
Experience with working in DevOps environment like GitHub, CI/CD pipelines
Excellent problem-solving abilities with a keen eye for detail are highly valued
ACADEMIC CREDENTIALS
Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
LOCATION
Markham, ON
This role is not eligible for visa sponsorship.
#LI-AJ1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
As the semiconductor industry pivots toward complex chiplet architectures and hyper-dense data center accelerators, the economics of quality necessitate shifting validation earlier in the production lifecycle. We are seeking a visionary Lead/Principal Diagnostics Engineer to drive our shift from proven post-silicon software validation frameworks and System-Level Tests (SLT) directly into all manufacturing flows for our latest products..
THE PERSON
In this role, you will bridge the gap between platform-level software execution and traditional hardware-driven manufacturing test patterns. You will design the architecture, tooling, and translation methodologies required to pack, convert, and stream complex software-driven GFX and compute test cases into robust, production-grade patterns used across all manufacturing insertions. This is a high-impact role requiring deep knowledge of system software/hardware interactions, graphics IP mechanics, and high-volume structural/functional manufacturing test domains.
KEY RESPONSIBILTIIES
Strategic Technical Leadership: Define the technical roadmap, architecture, and deployment strategy for migrating post-silicon SLT and functional GFX IP feature diagnostics onto various testing and validation platforms
Pattern Generation & Conversion: Architect and develop software utilities/pipelines to convert functional diagnostic sequences, register configurations, and compute workloads into cycle-accurate vector formats (e.g., STIL, WGL, or proprietary tester formats) compatible with modern testers.
Cross-Domain Collaboration: Serve as the primary technical liaison between the GFX/Compute Diagnostics team, Product/Test Engineering, and Design-for-Test (DFT) teams, analyzing and root causing RTL bugs and improving pre-silicon coverage
Platform Integration & Emulation: Analyze existing platform-level hardware/software dependencies (such as sideband management interfaces, firmware, and power management behaviors) to build deterministic, tester-friendly models that emulate host behaviors on multiple hardware platforms
Test Coverage & Cost Optimization: Optimize tester execution times (test cost reduction) while maximizing structural and functional test coverage for data center GPU IPs, focusing on massively parallel compute pipelines, high-bandwidth memory (HBM) controllers, and matrix math engines.
PREFERRED EXPERIENCE
Experience: Proven industry experience in silicon engineering spanning post-silicon validation, product engineering, diagnostics development, or structural/functional test generation.
Platform HW/SW Proficiency: Strong programming background in C/C++ and Python, with a concrete understanding of bare-metal or driver-level programming, registers, firmware interactions, and system memory maps
Pattern Flow Knowledge: Expert understanding of structural pattern generation, vector timing, clock domains, and diagnostic patterns (such as functional vectors, BIST/MBIST, or scan compression output).
Familiarity with high-volume manufacturing challenges unique to data center architectures, including high-power profiles, HBM integration, and multi-die chiplet interconnect protocols (e.g., UCIe, proprietary fabrics).
Deep understanding of GFX and compute architectures, with proven ability to design and implement diagnostic and test cases that maximize coverage and proactively identify silicon issues early
Understanding of AI/ML principles and some experience in applying LLM & ML models in applications
Experience with working in DevOps environment like GitHub, CI/CD pipelines
Excellent problem-solving abilities with a keen eye for detail are highly valued
ACADEMIC CREDENTIALS
Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
LOCATION
Markham, ON
This role is not eligible for visa sponsorship.
#LI-AJ1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
