THE PERSON
The ideal candidate will have strong expertise in formal verification for complex processor architectures and demonstrate the ability to execute and lead formal verification across the designs. Strong communication and cross-functional collaboration skills are essential to drive innovation and adoption of formal methods across AMD.
KEY RESPONSIBILITIES
Architect and execute formal verification methodologies to comprehensively cover CPU design, including datapath and control logic.
Scale formal verification to large, critical designs to ensure bug-free quality across the IP lifecycle.
Resolve convergence challenges using advanced techniques such as proof by induction, COI reduction and abstraction.
Build and maintain best-in-class formal verification infrastructure for adoption across engineering teams.
Explore formalization of ISA and memory models for CPU IP.
Stay at the forefront of formal verification innovation and foster technical relationships across AMD’s design community and EDA partners.
Champion cross-department collaboration and drive AMD-wide formal verification excellence.
PREFERRED EXPERIENCE
Hands-on experience of development of Assertion IP(AIP) and end-to-end properties is highly desirable
Strong debug skills for uArch functional failures
Advanced user of formal tools from academia and EDA vendors (e.g., JasperGold, VC Formal).
Proven success in delivering high-quality verification for large-scale processor designs under tight schedules.
Strong understanding of computer architecture and CPU pipelines.
Experience developing infrastructure for FPV, FXP(x-prop), DPV, SEC and other formal apps is highly desirable.
ACADEMIC CREDENTIALS
Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-PL1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
AMD is seeking an experienced Formal Verification Engineer, a technical leader passionate about advancing formal verification techniques for next-generation CPU IP design. This Individual will drive and execute AMD’s formal verification methodology across the CPU domain, ensuring industry-leading verification quality and productivity under aggressive timelines. The role involves close collaboration with architecture, design, and central formal verification teams to shape the roadmap, methodology, infrastructure, and execution of formal verification practices.
You will join a core team of elite industry experts working on cutting-edge and rapidly evolving CPU IP technologies.
THE PERSON
The ideal candidate will have strong expertise in formal verification for complex processor architectures and demonstrate the ability to execute and lead formal verification across the designs. Strong communication and cross-functional collaboration skills are essential to drive innovation and adoption of formal methods across AMD.
KEY RESPONSIBILITIES
Architect and execute formal verification methodologies to comprehensively cover CPU design, including datapath and control logic.
Scale formal verification to large, critical designs to ensure bug-free quality across the IP lifecycle.
Resolve convergence challenges using advanced techniques such as proof by induction, COI reduction and abstraction.
Build and maintain best-in-class formal verification infrastructure for adoption across engineering teams.
Explore formalization of ISA and memory models for CPU IP.
Stay at the forefront of formal verification innovation and foster technical relationships across AMD’s design community and EDA partners.
Champion cross-department collaboration and drive AMD-wide formal verification excellence.
PREFERRED EXPERIENCE
Hands-on experience of development of Assertion IP(AIP) and end-to-end properties is highly desirable
Strong debug skills for uArch functional failures
Advanced user of formal tools from academia and EDA vendors (e.g., JasperGold, VC Formal).
Proven success in delivering high-quality verification for large-scale processor designs under tight schedules.
Strong understanding of computer architecture and CPU pipelines.
Experience developing infrastructure for FPV, FXP(x-prop), DPV, SEC and other formal apps is highly desirable.
ACADEMIC CREDENTIALS
Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-PL1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
