KEY RESPONSIBLITIES
Collaborate with a dedicated team of engineers to define and implement CPL microarchitecture for AMD CPUs.
Reliably deliver a design from concept through tapeout by innovating through complex and challenging requirements.
Drive design closure gaining experience with Static Timing, CDC/Gate CDC, and Static Power analysis.
Identify customer challenges and insert a compelling AMD value proposition to address challenges.
Make technical contributions and innovations that enable high performance, high frequency, and power efficiency on caches, fabrics, and interfaces of our server, desktop, and laptop CPUs.
PREFERRED EXPERIENCE
Proficiency with Verilog HDL, Clock/Power Domain Crossing concepts, and Power Management concepts.
Understanding of modern CPU architecture - prior experience designing shared cache or last level cache and related IPs a plus.
Eagerness to learn and grow as a CPL design engineer.
Collaborate effectively towards the success of the project by working closely with logic design, physical design and verification teamates across the wider organization.
Demonstrate a responsive track record of engaging with a diverse set of teams and across a broad set of technical areas to facilitate design delivery.
ACADEMIC CREDENTIALS
Bachelors or Masters degree in computer engineering/Electrical Engineering
LOCATION
Dublin or Cork, Ireland.
#LI-PL1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
As a CPL (Chip Pervasive Logic) CPU Architect/RTL Design Engineer , you will have an outstanding opportunity to drive the definition, implementation (RTL design), and integration of Clocking, Reset and Power in AMD’s next-generation caches/core. You will work as part of an experienced, skilled, and motivated engineering team with a track record of success. You will help make AMD’s ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology.
THE PERSON
You approach challenges relentlessly with both critical thinking and creativity. You work as part of a team with strong communication and collaboration skills. You have a proven understanding of modern CPU architecture and have ideas and/or drive to make it even better. Does this describe you? If so, then join us
KEY RESPONSIBLITIES
Collaborate with a dedicated team of engineers to define and implement CPL microarchitecture for AMD CPUs.
Reliably deliver a design from concept through tapeout by innovating through complex and challenging requirements.
Drive design closure gaining experience with Static Timing, CDC/Gate CDC, and Static Power analysis.
Identify customer challenges and insert a compelling AMD value proposition to address challenges.
Make technical contributions and innovations that enable high performance, high frequency, and power efficiency on caches, fabrics, and interfaces of our server, desktop, and laptop CPUs.
PREFERRED EXPERIENCE
Proficiency with Verilog HDL, Clock/Power Domain Crossing concepts, and Power Management concepts.
Understanding of modern CPU architecture - prior experience designing shared cache or last level cache and related IPs a plus.
Eagerness to learn and grow as a CPL design engineer.
Collaborate effectively towards the success of the project by working closely with logic design, physical design and verification teamates across the wider organization.
Demonstrate a responsive track record of engaging with a diverse set of teams and across a broad set of technical areas to facilitate design delivery.
ACADEMIC CREDENTIALS
Bachelors or Masters degree in computer engineering/Electrical Engineering
LOCATION
Dublin or Cork, Ireland.
#LI-PL1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
