Drive verification planning and execution at full-chip SoC levels.
Establish clear verification milestones aligned with RTL development and tape-out schedules.
Drive verification quality, predictability, efficiency, and reuse across semiconductor programs.
Verification Methodology & Technical Leadership
Provide technical leadership for C/C++/ASM/SystemVerilog/UVM-based constrained-random verification.
Guide development of scalable and reusable testbench architectures, verification components, sequences, scoreboards, checkers, reference models, and coverage models.
Drive coverage-based verification methodology using functional coverage, code coverage, assertions, and verification-plan closure.
Establish methodologies for IP-to-subsystem-to-SoC verification reuse.
Verification Execution & Sign-Off
Own verification execution across multiple ASIC programs and development milestones.
Establish measurable RTL verification sign-off criteria.
Drive closure of verification plans, functional coverage, code coverage, assertion coverage, and regressions. Appropriately drive verification matrix.
Organization & People Leadership
Build, lead, and develop a high-performing ASIC RTL verification organization.
Recruit and retain verification engineers, technical leads, verification architects, and engineering managers.
Establish clear technical ownership and accountability across IP, subsystem, and SoC verification.
Mentor senior engineers and develop future technical and management leaders.
Cross-Functional Collaboration
Partner closely with
DV teams across GEO
SoC/System Architecture
Microarchitecture
RTL Design
IP Design and Verification teams
CAD/EDA Infrastructure
Program Management
Firmware/Software teams where required for RTL verification
Drive alignment on specifications, verification requirements, dependencies, schedules, quality metrics, and RTL sign-off criteria.
Required Qualifications
BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
17+ years of ASIC/SoC RTL verification experience, with significant technical and people leadership responsibility.
Proven track record leading verification of complex semiconductor products through RTL sign-off and tape-out.
Strong understanding of clock/reset architectures, interrupts, register interfaces, memory interfaces, and power-management functionality from an RTL verification perspective.
Demonstrated ability to lead verification across multiple projects and geographically distributed teams.
Strong engineering judgment and ability to make data-driven RTL sign-off decisions.
Excellent communication, organizational, and leadership skills.
Preferred Qualifications
Experience verifying multi-core or multi-engine SoCs with complex interconnect and memory architectures.
Experience with protocols such as PCIe, CXL, Ethernet, DDR/LPDDR, USB, or other high-speed interfaces relevant to the product.
Experience with X86 and ARM processor subsystems.
Experience in ARM based and X86 based SOC.
Has understanding of GFX/GPU based SOC.
Experience developing reusable UVM verification IP and environments.
Experience with low-power RTL verification, including UPF-driven simulation where applicable.
Strong scripting and automation experience using Python or similar languages.
Experience establishing verification methodologies and infrastructure across multiple semiconductor product generations.
#LI-AB1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
SENIOR MANAGER SILICON DESIGN ENGINEER
Position Overview
Sr Manager of ASIC RTL Design Verification is to lead the pre-silicon functional verification organization.
He will own the RTL verification strategy, methodology, execution, and sign-off at SoC levels. The role requires deep technical expertise in c/c++/ASM SystemVerilog/UVM-based verification, strong understanding of digital RTL and SoC architectures, and demonstrated experience building and leading high-performing verification teams.
He will work closely with RTL design, architecture, and program management teams to deliver high-quality, functionally correct RTL and achieve predictable tape-out schedules.
Key Responsibilities
RTL Verification Leadership
Own end-to-end RTL functional verification for ASIC/SoC programs from specification through RTL sign-off.
Define verification strategy, architecture, methodology, execution plans, and sign-off criteria.
Drive verification planning and execution at full-chip SoC levels.
Establish clear verification milestones aligned with RTL development and tape-out schedules.
Drive verification quality, predictability, efficiency, and reuse across semiconductor programs.
Verification Methodology & Technical Leadership
Provide technical leadership for C/C++/ASM/SystemVerilog/UVM-based constrained-random verification.
Guide development of scalable and reusable testbench architectures, verification components, sequences, scoreboards, checkers, reference models, and coverage models.
Drive coverage-based verification methodology using functional coverage, code coverage, assertions, and verification-plan closure.
Establish methodologies for IP-to-subsystem-to-SoC verification reuse.
Verification Execution & Sign-Off
Own verification execution across multiple ASIC programs and development milestones.
Establish measurable RTL verification sign-off criteria.
Drive closure of verification plans, functional coverage, code coverage, assertion coverage, and regressions. Appropriately drive verification matrix.
Organization & People Leadership
Build, lead, and develop a high-performing ASIC RTL verification organization.
Recruit and retain verification engineers, technical leads, verification architects, and engineering managers.
Establish clear technical ownership and accountability across IP, subsystem, and SoC verification.
Mentor senior engineers and develop future technical and management leaders.
Cross-Functional Collaboration
Partner closely with
DV teams across GEO
SoC/System Architecture
Microarchitecture
RTL Design
IP Design and Verification teams
CAD/EDA Infrastructure
Program Management
Firmware/Software teams where required for RTL verification
Drive alignment on specifications, verification requirements, dependencies, schedules, quality metrics, and RTL sign-off criteria.
Required Qualifications
BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
17+ years of ASIC/SoC RTL verification experience, with significant technical and people leadership responsibility.
Proven track record leading verification of complex semiconductor products through RTL sign-off and tape-out.
Strong understanding of clock/reset architectures, interrupts, register interfaces, memory interfaces, and power-management functionality from an RTL verification perspective.
Demonstrated ability to lead verification across multiple projects and geographically distributed teams.
Strong engineering judgment and ability to make data-driven RTL sign-off decisions.
Excellent communication, organizational, and leadership skills.
Preferred Qualifications
Experience verifying multi-core or multi-engine SoCs with complex interconnect and memory architectures.
Experience with protocols such as PCIe, CXL, Ethernet, DDR/LPDDR, USB, or other high-speed interfaces relevant to the product.
Experience with X86 and ARM processor subsystems.
Experience in ARM based and X86 based SOC.
Has understanding of GFX/GPU based SOC.
Experience developing reusable UVM verification IP and environments.
Experience with low-power RTL verification, including UPF-driven simulation where applicable.
Strong scripting and automation experience using Python or similar languages.
Experience establishing verification methodologies and infrastructure across multiple semiconductor product generations.
#LI-AB1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
