KEY RESPONSIBILITIES
Architect and design key blocks for next-generation DPU ASICs targeting AI networking workloads
Contribute across the full ASIC development lifecycle
architecture definition
microarchitecture and RTL design
design reviews
implementation support
tapeout
silicon bring-up
production ramp and mass deployment support
Collaborate on advanced network processing engines, including P4-based, protocol-independent packet processing solutions
Design and implement high-speed, complex ASIC blocks for networking and data movement applications
Work closely with verification, modeling, software, and hardware teams to ensure functional correctness and system-level performance
Debug and resolve issues across simulation, emulation, lab bring-up, and post-silicon phases
Contribute to performance, power, and area optimization
Support integration of ASIC IPs into larger SoC and system architectures
Produce high-quality design documentation and participate in technical reviews
REQUIRED QUALIFICATIONS
Seasoned ASIC design experience
Proven hands-on experience developing high-speed, complex ASICs
Strong experience across the complete ASIC development cycle, from RTL architecture to tapeout to mass production
Solid background in networking and packet-processing architectures
Experience collaborating across
Verification
Modeling
Software
Hardware/system teams
Strong RTL design skills in
Verilog
SystemVerilog
Strong programming skills in
C/C++
Scripting experience in
Python
Tcl
Shell
PREFERRED QUALIFICATIONS
Experience designing complex ARM- or RISC-V-based SoC ASICs
Hands-on experience building complex Network-on-Chip (NoC) architectures
Strong knowledge of AXI / AMBA protocols
Familiarity with P4, programmable packet-processing pipelines, or protocol-independent networking architectures
Experience with post-silicon debug, bring-up, and production support
Experience with high-performance interconnect, data movement, and SoC integration
Self-motivated engineer with strong ownership and execution skills
Strong problem-solving ability and willingness to take on new technical challenges
Continuous learner who thrives in a fast-moving environment
Excellent communication and cross-functional collaboration skills
ACADEMIC CREDENTIALS
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
LOCATION
Santa Clara, CA
#LI-NP1
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE TEAM
Our group, NTSG, develops advanced system solutions that combine ASIC, hardware, and software to enable next-generation AI networking workloads. We are building highly integrated, high-performance networking systems and are looking for experienced ASIC engineers to help drive development from architecture through production.
THE ROLE
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development cycle — from RTL architecture and design through tapeout, silicon bring-up, and mass production.
THE PERSON
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development cycle — from RTL architecture and design through tapeout, silicon bring-up, and mass production.
KEY RESPONSIBILITIES
Architect and design key blocks for next-generation DPU ASICs targeting AI networking workloads
Contribute across the full ASIC development lifecycle
architecture definition
microarchitecture and RTL design
design reviews
implementation support
tapeout
silicon bring-up
production ramp and mass deployment support
Collaborate on advanced network processing engines, including P4-based, protocol-independent packet processing solutions
Design and implement high-speed, complex ASIC blocks for networking and data movement applications
Work closely with verification, modeling, software, and hardware teams to ensure functional correctness and system-level performance
Debug and resolve issues across simulation, emulation, lab bring-up, and post-silicon phases
Contribute to performance, power, and area optimization
Support integration of ASIC IPs into larger SoC and system architectures
Produce high-quality design documentation and participate in technical reviews
REQUIRED QUALIFICATIONS
Seasoned ASIC design experience
Proven hands-on experience developing high-speed, complex ASICs
Strong experience across the complete ASIC development cycle, from RTL architecture to tapeout to mass production
Solid background in networking and packet-processing architectures
Experience collaborating across
Verification
Modeling
Software
Hardware/system teams
Strong RTL design skills in
Verilog
SystemVerilog
Strong programming skills in
C/C++
Scripting experience in
Python
Tcl
Shell
PREFERRED QUALIFICATIONS
Experience designing complex ARM- or RISC-V-based SoC ASICs
Hands-on experience building complex Network-on-Chip (NoC) architectures
Strong knowledge of AXI / AMBA protocols
Familiarity with P4, programmable packet-processing pipelines, or protocol-independent networking architectures
Experience with post-silicon debug, bring-up, and production support
Experience with high-performance interconnect, data movement, and SoC integration
Self-motivated engineer with strong ownership and execution skills
Strong problem-solving ability and willingness to take on new technical challenges
Continuous learner who thrives in a fast-moving environment
Excellent communication and cross-functional collaboration skills
ACADEMIC CREDENTIALS
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
LOCATION
Santa Clara, CA
#LI-NP1
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
