Track and report coverage closure, bug metrics, and sign-off readiness.
Participate in design and verification reviews.
Required Qualifications
Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering (or equivalent).
Strong proficiency in SystemVerilog and the UVM methodology.
Solid understanding of digital design fundamentals, RTL (Verilog/VHDL), and synthesis concepts.
Experience with constrained-random, coverage-driven verification and assertion-based verification (SVA).
Proficiency with industry simulation/debug tools (e.g., Cadence Xcelium/SimVision, Synopsys VCS/Verdi, or equivalent).
Scripting skills (Python, Perl, Tcl, or shell) for automation and flow development.
Strong problem-solving, debugging, and communication skills.
Preferred / Nice-to-Have
Experience with mixed-signal verification (Verilog-AMS, real-number modeling / wreal).
Familiarity with functional safety (ISO 26262) and/or automotive quality (AEC-Q100) requirements.
Exposure to formal verification methods and tools.
Experience with low-power verification (UPF/CPF).
Knowledge of sensor, motor driver, or power management IC architectures.
Experience with version control (Git) and CI/CD for verification regressions.
Why Allegro?
Join Allegro and become part of a team where your contributions truly matter.
We foster a culture of Real Innovation, empowering you to push boundaries, develop cutting-edge solutions, and drive continuous improvement.
Your work will create a Real Impact by solving complex real-world challenges that fuel our success and shape the future of technology.
You’ll experience Real Connection, collaborating with talented colleagues around the globe in an environment built on trust, respect, and a shared purpose.
Join us—and help build what’s next.
